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Center of Excellence Cognitive Interaction Technology

Publications

2016
  • Hesse, Marc; Christ, Peter; Hörmann, Timm; Adams, Michael; Rückert, Ulrich; Fichtner, Ina:
    Die Entwicklung zukünftiger körpernaher Sensorsysteme für die autarke und mobile Trainingsunterstützung.
    In: Schriftenreihe Angewandte Trainingswissenschaft, Volume: 4, 17. Frühjahrsschule "Technologien im Leistungssport", Meyer & Meyer, 2016. »»
    Fulltext (external)

    conference paper / id: 2903244

  • Sievers, Gregor:
    Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen.
    In: Universität Bielefeld, 2016. »»
    Fulltext (PDF) Abstract

    thesis / id: 2904773

    Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen

    Sievers, Gregor

    Eingebettete mikroelektronische Systeme finden in vielen Bereichen des täglichen Lebens Anwendung. Die Integration von zunehmend mehr Prozessorkernen auf einem einzelnen Mikrochip (On-Chip-Multiprozessor, MPSoC) erlaubt eine Steigerung der Rechenleistung und der Ressourceneffizienz dieser Systeme. In der AG Kognitronik und Sensorik der Universität Bielefeld wird das CoreVA-MPSoC entwickelt, welches ressourceneffiziente VLIW-Prozessorkerne über eine hierarchische Verbindungsstruktur koppelt. Eine enge Kopplung mehrerer Prozessorkerne in einem Cluster ermöglicht hierbei eine breitbandige Kommunikation mit geringer Latenz.<br /><br /> Der Hauptbeitrag der vorliegenden Arbeit ist die Entwicklung und Entwurfsraumexploration eines ressourceneffizienten CPU-Clusters für den Einsatz im CoreVA-MPSoC. Eine abstrakte Modellierung der Hardware- und Softwarekomponenten des CPU-Clusters sowie ein hoch automatisierter Entwurfsablauf ermöglichen die schnelle Analyse eines großen Entwurfsraums. Im Rahmen der Entwurfsraumexploration werden verschiedene Topologien, Busstandards und Speicherarchitekturen untersucht. Insbesondere das Zusammenspiel der Hardware-Architektur mit Programmiermodell und Synchronisierung ist evident für eine hohe Ressourceneffizienz und eine gute Ausnutzung der verfügbaren Rechenleistung durch den Anwendungsentwickler. Dazu wird ein an die Hardwarearchitektur angepasstes blockbasiertes Synchronisierungsverfahren vorgestellt. Dieses Verfahren wird von Compilern für die Sprachen StreamIt, C sowie OpenCL verwendet, um Anwendungen auf verschiedenen Konfigurationen des CPU-Clusters abzubilden. Neun repräsentative Streaming-Anwendungen zeigen bei der Abbildung auf einem Cluster mit 16 CPUs eine durchschnittliche Beschleunigung um den Faktor 13,3 gegenüber der Ausführung auf einer CPU. Zudem wird ein eng gekoppelter gemeinsamer L1-Datenspeicher mit mehreren Speicherbänken in den CPU-Cluster integriert, der allen CPUs einen Zugriff mit geringer Latenz erlaubt. Des Weiteren wird die Verwendung verschiedener Instruktionsspeicher und -caches evaluiert sowie der Energiebedarf für Kommunikation und Synchronisierung im CPU-Cluster betrachtet.<br /><br /> Es wird in dieser Arbeit gezeigt, dass ein CPU-Cluster mit 16 CPU-Kernen einen guten Kompromiss in Bezug auf den Flächenbedarf der Cluster-Verbindungsstruktur sowie die Leistungsfähigkeit des Clusters darstellt. Ein CPU-Cluster mit 16 2-Slot-VLIW-CPUs und insgesamt 512 kB Speicher besitzt bei einer prototypischen Implementierung in einer 28-nm-FD-SOI-Standardzellenbibliothek einen Flächenbedarf von 2,63 mm². Bei einer Taktfrequenz von 760 MHz liegt die durchschnittliche Leistungsaufnahme bei 440 mW. Eine FPGA-basierte Emulation auf einem Xilinx Virtex-7-FPGA erlaubt die Evaluierung eines CoreVA-MPSoCs mit bis zu 24 CPUs bei einer maximalen Taktfrequenz von bis zu 124 MHz. Als weiteres Anwendungsszenario wird ein CoreVA-MPSoC mit bis zu vier CPUs auf das FPGA des autonomen Miniroboters AMiRo abgebildet.


    In: Universität Bielefeld, 2016.
  • Herbrechtsmeier, Stefan; Korthals, Timo; Schöpping, Thomas; Rückert, Ulrich:
    AMiRo: A Modular & Customizable Open-Source Mini Robot Platform.
    In: 20th International Conference on System Theory, Control and Computing, 2016. »»
    Abstract

    conference paper / id: 2906483

    AMiRo: A Modular & Customizable Open-Source Mini Robot Platform

    Herbrechtsmeier, Stefan; Korthals, Timo; Schöpping, Thomas; Rückert, Ulrich

    AMiRo is a novel modular robot platform that can be easily extended and customized in hardware and software. Built up of electronic modules that fully exploit recent technology and open-source software for sensor processing, actuator control, and cognitive processing, the robot facilitates rich autonomous behaviors. Further contribution lies in the completely open- source software habitat: from low-level microcontroller imple- mentations, over high-level applications running on an embedded processor, up to hardware accelerated algorithms using pro- grammable logic. This paper describes in detail the motivation, system architecture, and software design of the AMiRo, which surpasses state-of-the-art competitors.


    In: 20th International Conference on System Theory, Control and Computing, 2016.
  • Korthals, Timo; Barther, Marvin; Schöpping, Thomas; Herbrechtsmeier, Stefan; Rückert, Ulrich:
    Occupancy Grid Mapping with Highly Uncertain Range Sensors based on Inverse Particle Filters.
    In: Proceedings of the 13th International Conference on Informatics in Control, Automation and Robotics, 13th International Conference on Informatics in Control, Automation and Robotics, 2016. »»
    Abstract

    conference paper / id: 2906482

    Occupancy Grid Mapping with Highly Uncertain Range Sensors based on Inverse Particle Filters

    Korthals, Timo; Barther, Marvin; Schöpping, Thomas; Herbrechtsmeier, Stefan; Rückert, Ulrich

    A huge number of techniques for detecting and mapping obstacles based on LIDAR and SONAR exist, though not taking approximative sensors with high levels of uncertainty into consideration. The proposed mapping method in this article is undertaken by detecting surfaces and approximating objects by distance using sensors with high localization ambiguity. Detection is based on an Inverse Particle Filter, which uses readings from single or multiple sensors as well as a robot’s motion. This contribution describes the extension of the Sequential Importance Resampling filter to detect objects based on an analytical sensor model and embedding into Occupancy Grid Maps. The approach has been applied to the autonomous mini robot AMiRo in a distributed way. There were promising results for its low-power, low-cost proximity sensors in various real life mapping scenarios, which outperform the standard Inverse Sensor Model approach.


    In: Proceedings of the 13th International Conference on Informatics in Control, Automation and Robotics, 13th International Conference on Informatics in Control, Automation and Robotics, 2016.
  • Schöpping, Thomas; Korthals, Timo; Herbrechtsmeier, Stefan; Chinapirom, Teerapat; Abel, Robert; Barther, Marvin; Kenneweg, Tristan; Braun, Claas; Rückert, Ulrich:
    AMiRo-OS.
    In: Bielefeld University, 2016. »»
    Fulltext (PDF) Abstract

    thesis / id: 2902276

    AMiRo-OS

    Schöpping, Thomas; Korthals, Timo; Herbrechtsmeier, Stefan; Chinapirom, Teerapat; Abel, Robert; Barther, Marvin; Kenneweg, Tristan; Braun, Claas; Rückert, Ulrich

    [AMiRo-OS](https://opensource.cit-ec.de/projects/amiro-os) is the operating system for the base version of the Autonomous Mini Robot (AMiRo). It utilizes [ChibiOS](http://chibios.org) (a real-time operating system for embedded devices developed by Giovanni di Sirio) as system kernel and extends it with platform specific functionalities. It also comprises a bootloader and flashing toolchain, based on [OpenBLT](http://feaser.com/en/openblt.php).


    In: Bielefeld University, 2016.
  • Korthals, Timo; Skiba, Andreas; Krause, Thilo; Jungeblut, Thorsten; Ruckelshausen, Arno; Meyer-Aurich, Andreas; Rath, Thomas; Recke, Guido; Theuvsen, Brigitte:
    Evidenzkarten-basierte Sensorfusion zur Umfelderkennung und Interpretation in der Ernte.
    In: Informatik in der Land-, Forst- und Ernährungswirtschaft - Intelligente Systeme - Stand der Technik und neue Möglichkeiten, GIL-Jahrestagung, 2016. »»
    Fulltext (PDF)

    conference paper / id: 2902860

  • Hörmann, Timm; Hesse, Marc; Christ, Peter; Adams, Michael; Menßen, Christian; Rückert, Ulrich:
    Fine-Grained Prediction of Cognitive Workload in a Modern Working Environment by Utilizing Short-Term Physiological Parameters.
    In: Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies, Volume: 4, 9th International Joint Conference on Biomedical Engineering Systems and Technologies, SCITEPRESS, 2016. »»

    Fine-Grained Prediction of Cognitive Workload in a Modern Working Environment by Utilizing Short-Term Physiological Parameters

    Hörmann, Timm; Hesse, Marc; Christ, Peter; Adams, Michael; Menßen, Christian; Rückert, Ulrich

    In this paper we present a method to predict cognitive workload during the interaction with a tablet computer. To set up a predictor that estimates the reflected self-reported cognitive workload we analyzed the information gain of heart rate, electrodermal activity and user input (touch) based features. From the derived optimal feature set we present a Gaussian Process based learner that enables fine-grained and short term detection of cognitive workload. Average inter-subject accuracy in 10-fold cross validation is 74.1 % for the fine-grained 5-class problem and 96.0 % for the binary class problem.


    In: Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies, Volume: 4, 9th International Joint Conference on Biomedical Engineering Systems and Technologies, SCITEPRESS, 2016.
  • Flasskamp, Martin; Sievers, Gregor; Ax, Johannes; Klarhorst, Christian; Jungeblut, Thorsten; Kelly, Wayne; Thies, Michael; Porrmann, Mario:
    Performance Estimation of Streaming Applications for Hierarchical MPSoCs.
    In: Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), ACM Press, 2016. »»
    Fulltext (PDF)

    conference paper / id: 2900363

  • Kragh, Mikkel; Christiansen, Peter; Korthals, Timo; Jungeblut, Thorsten; Karstoft, Henrik; Jørgensen, Rasmus N.:
    Multi-Modal Obstacle Detection and Evaluation of Occupancy Grid Mapping in Agriculture.
    In: International Conference on Agricultural Engineering, CIGR - AgEng 2016, International Commission of Agricultural and Biosystems Engineering, 2016. »»
    Fulltext (external) Abstract

    conference paper / id: 2906479

    Multi-Modal Obstacle Detection and Evaluation of Occupancy Grid Mapping in Agriculture

    Kragh, Mikkel; Christiansen, Peter; Korthals, Timo; Jungeblut, Thorsten; Karstoft, Henrik; Jørgensen, Rasmus N.

    In recent years, mapping and automation has been increasingly investigated and applied in precision agriculture. The ultimate goal of this development is to apply autonomous vehicles operating efficiently without any human intervention. Such autonomous operation imposes severe safety hazards, demanding accurate and robust risk detection, and avoidance systems. It is unlikely that one sensor can single­handedly guarantee this, and therefore multiple sensing modalities are often combined in order to increase detection performance and introduce redundancy. In this paper, we present a global mapping approach utilizing diverse sensor technologies to achieve a uniform obstacle interpretation of the environment. Using occupancy grid maps, we fuse information from a monocular color camera, a RADAR, and a LIDAR in combination with IMU­assisted GPS­positioning. For each sensor, we present detection algorithms, mapping from raw sensor data to a 2D grid­based obstacle interpretation of the environment. These are then fused temporally with the occupancy grid algorithm, and afterwards spatially in a competitive and complementary way to produce a combined global obstacle map. The method is evaluated on an extensive dataset recorded at Research Centre Foulum, Denmark, in June 2015. The dataset comprises sensor data from a tractor­mounted recording system in a grass mowing scenario with various obstacles. A ground truth map has been obtained with a mapping drone. Results show promising obstacle detection capabilities and an increase in performance when fusing information across sensor modalities and layers. The proposed mapping framework is able to fuse a vast amount of information across a diverse sensor set, using an efficient and novel approach for obstacle detection in agriculture.


    In: International Conference on Agricultural Engineering, CIGR - AgEng 2016, International Commission of Agricultural and Biosystems Engineering, 2016.
  • Hörmann, Timm; Hesse, Marc; Adams, Michael; Rückert, Ulrich:
    A Software Assistant for User-Centric Calibration of a Wireless Body Sensor.
    In: 2016 IEEE 13th International Conference on Wearable and Implantable Body Sensor Networks (BSN), 2016. »»

    A Software Assistant for User-Centric Calibration of a Wireless Body Sensor

    Hörmann, Timm; Hesse, Marc; Adams, Michael; Rückert, Ulrich

    Body sensors have a promising contribution to health promotion in many areas of daily life (telemedicine, corporate health care or recreational sports). However, the valid measurement of vital signs and kinematic data strongly depends on the signals' quality and the users' compliance (proper usage). Although, there is a lot of research work concerning accuracy and calibration of wireless body sensors the human user is typically not involved. Thus, in this work, we present a software assistant (wizard) that guides users during the process of attaching and setting up a wireless body sensor. Furthermore, insights of the implemented software as well as the utilized quality measures and calibration steps are given (ECG, respiration sensor and accelerometer). With the proposed software assistant, the users are instructed to correctly attach the body sensor and calibrate or verify the operability of the various sensor elements. The primary goal is to encourage compliance and the users' sense of control. In this way, we want to reduce faulty operation and ensure optimal signal quality.


    In: 2016 IEEE 13th International Conference on Wearable and Implantable Body Sensor Networks (BSN), 2016.
  • Meyer zu Borgsen, Sebastian; Korthals, Timo; Lier, Florian; Wachsmuth, Sven; Behnke, Sven; Lee, Daniel D.; Sariel, Sanem; Sheh, Raymond:
    ToBI – Team of Bielefeld: Enhancing Robot Behaviors and the Role of Multi-Robotics in RoboCup@Home.
    In: RoboCup 2016, Volume: 9776, Springer, 2016. »»

    book chapter / id: 2906480

  • Christ, Peter:
    Detektion und Analyse physiologischer und biokinematischer Parameter mit Körpersensoren.
    In: Universität Bielefeld, 2016. »»
    Fulltext (PDF)

    thesis / id: 2900412

  • Hesse, Marc; Adams, Michael; Hörmann, Timm; Rückert, Ulrich:
    Towards a Comprehensive Power Consumption Model for Wireless Sensor Nodes.
    In: 2016 IEEE 13th International Conference on Wearable and Implantable Body Sensor Networks (BSN), 2016. »»

    Towards a Comprehensive Power Consumption Model for Wireless Sensor Nodes

    Hesse, Marc; Adams, Michael; Hörmann, Timm; Rückert, Ulrich

    Energy efficiency is the most outstanding design criterion for wireless sensor nodes and especially wireless body sensors. Because a detailed measurement of the system's power consumption is not possible during the design process and often too complex for already manufactured devices, the power consumption has to be estimated. This leads to the need for a comprehensive and modular model for the power consumption of WSNs, which is proposed in this work. Due to the modular structure of the model the user is able to get a first estimate in an early stage of the design process (e.g. choose components) and to get a more accurate estimation later in the design process by lowering the abstraction level. This tackles the demanding trade-off between accuracy and usability in modeling.


    In: 2016 IEEE 13th International Conference on Wearable and Implantable Body Sensor Networks (BSN), 2016.
  • Korthals, Timo; Skiba, Andreas; Krause, Thilo:
    Einsatz Event-Basierter Systemarchitektur für Erntemaschinen zur Elektronischen Umfelderkennung.
    In: 74. Internationale Land.Technik, 2016. »»

    conference paper / id: 2906484

  • Kierzynka, Michal; Kosmann, Lars; vor dem Berge, Micha; Krupop, Stefan; Hagemeyer, Jens; Griessl, René; Peykanu, Meysam; Oleksiak, Ariel:
    Energy Efficiency of Sequence Alignment Tools - Software and Hardware Perspectives.
    In: Future Generation Computer Systems, Elsevier, 2016. »»
    Fulltext (external)

    article / id: 2903257

2015
  • Ax, Johannes; Buda, Aurel; Schneider, Daniel; Hartfiel, John; Dürkop, Lars; Jungeblut, Thorsten; Jasperneite, Jürgen; Vedral, Andreas; Rückert, Ulrich:
    Universelle Echtzeit-Ethernet Architektur zur Integration in rekonfigurierbare Automatisierungssysteme.
    In: 45. Jahrestagung der Gesellschaft für Informatik (INFORMATIK), 2015. »»

    conference paper / id: 2757836

  • Ax, Johannes; Flasskamp, Martin; Sievers, Gregor; Klarhorst, Christian; Jungeblut, Thorsten; Kelly, Wayne:
    An Abstract Model for Performance Estimation of the Embedded Multiprocessor CoreVA-MPSoC Technical Report (v1.0).
    In: 2015. »»
    Fulltext (PDF)

    report / id: 2783874

  • Sievers, Gregor; Ax, Johannes; Kucza, Nils; Flasskamp, Martin; Jungeblut, Thorsten; Kelly, Wayne; Porrmann, Mario; Rückert, Ulrich:
    Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI.
    In: 2015 IEEE International Symposium on Circuits & Systems (ISCAS), 2015 IEEE International Symposium on Circuits & Systems (ISCAS), IEEE, 2015. »»
    Fulltext (external) Abstract

    conference paper / id: 2732427

    Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI

    Sievers, Gregor; Ax, Johannes; Kucza, Nils; Flasskamp, Martin; Jungeblut, Thorsten; Kelly, Wayne; Porrmann, Mario; Rückert, Ulrich

    Embedded many-core architectures contain dozens to hundreds of CPU cores that are connected via a highly scalable NoC interconnect. Our Multiprocessor-System-on-Chip CoreVA-MPSoC combines the advantages of tightly coupled bus-based communication with the scalability of NoC approaches by adding a CPU cluster as an additional level of hierarchy. In this work, we analyze different cluster interconnect implementations with 8 to 32 CPUs and compare them in terms of resource requirements and performance to hierarchical NoCs approaches. Using 28 nm FD-SOI technology the area requirement for 32 CPUs and AXI crossbar is 5.59 mm2 including 23.61% for the interconnect at a clock frequency of 830 MHz. In comparison, a hierarchical MPSoC with 4 CPU cluster and 8 CPUs in each cluster requires only 4.83 mm2 including 11.61% for the interconnect. To evaluate the performance, we use a compiler for streaming applications to map programs to the different MPSoC configurations. We use this approach for a design-space exploration to find the most efficient architecture and partitioning for an application.


    In: 2015 IEEE International Symposium on Circuits & Systems (ISCAS), 2015 IEEE International Symposium on Circuits & Systems (ISCAS), IEEE, 2015.
  • Hörmann, Timm; Christ, Peter; Hesse, Marc; Rückert, Ulrich:
    Robust Estimation of Physical Activity by Adaptively Fusing Multiple Parameters.
    In: Wearable and Implantable Body Sensor Networks (BSN), 2015 IEEE 12th International Conference on, 2015 IEEE International Conference on Body Sensor Networks (BSN), IEEE, 2015. »»
    Fulltext (PDF) Fulltext (external)

    conference paper / id: 2783152

  • Irwansyah, Arif; Ibraheem, Omar Waleed; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich:
    FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking.
    In: ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on, International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2015. »»
    Abstract

    conference paper / id: 2901108

    FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking

    Irwansyah, Arif; Ibraheem, Omar Waleed; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich

    Shape-based object detection and recognition are frequently used methods in the field of computer vision. A well-known algorithm for circle detection is the Circular Hough Transform (CHT). This Hough Transform algorithm needs a huge memory space and large computational resources. Field Programmable Gate Array (FPGA)-based hardware accelerators can be used to efficiently handle such compute-intensive applications. In this paper, we present a resource-efficient FPGA-based architecture for the CHT algorithm. Additionally, we introduce a unique approach by combining the CHT algorithm with graph clustering. The combination of these algorithms and their implementation on a Xilinx Virtex-4 FPGA is used to support real-time vision-based multi-robot tracking. Furthermore, an efficient architecture is proposed to significantly reduce the required memory in the CHT module. For the Graph Clustering module, a multiplier-less distance calculation unit is implemented, significantly reducing the required FPGA resources. The proposed CHT design can handle multi-robot localization with an accuracy of 97 %, supporting a maximum video resolution of 1024x1024 with 128 frames per second, resulting in 134 MPixel/s. Our design provides significantly higher throughput compared to other implementations on embedded processors, FPGAs, and general purpose CPUs. Compared to an OpenCV implementation on a 3.2 GHz desktop CPU, our implementation achieves a speed-up of more than 5.7.


    In: ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on, International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2015.
  • Korthals, Timo; Krause, Thilo; Rückert, Ulrich; Niggemann, Oliver; Beyerer, Jürgen:
    Evidence Grid Based Information Fusion for Semantic Classifiers in Dynamic Sensor Networks.
    In: Machine Learning for Cyber Physical Systems, International Conference ML4CPS 2015, Springer Science + Business Media, 2015. »»

    book chapter / id: 2902858

  • Buda, Aurel; Walter, Martin; Hartfiel, John; Ax, Johannes; Nussbaum, Konstantin; Jungeblut, Thorsten; Porrmann, Mario:
    Automatische Protokollanpassung von Echtzeit-Ethernet-Standards durch FPGA-Technologien.
    In: Automation 2015, 2015. »»

    conference paper / id: 2732419

  • Ibraheem, Omar Waleed; Irwansyah, Arif; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich:
    A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms.
    In: ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on, International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2015. »»
    Abstract

    conference paper / id: 2901107

    A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms

    Ibraheem, Omar Waleed; Irwansyah, Arif; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich

    In vision processing systems, many applications require multi-camera support. For the connection of the cameras to the processing system, multiple interfaces and a platform capable of handling sustained high data rates are essential. To cope with these requirements, a hardware-based solution using FPGA technology is advisable, especially when targeting space and energy constrained embedded systems. The aim of this work is to develop and implement an FPGA-based scalable and resourceefficient multi-camera GigE Vision IP core for video and image processing. To reduce the number of interfaces needed, the IP core supports the connection of multi-camera interfaces to a single Gigabit Ethernet port using an Ethernet switch. The multicamera GigE Vision IP core is able to extract the raw video data from multiple GigE Vision video streams, reconstruct the video frames from every camera and pass these data for further processing. To test the system, four GigE Vision cameras are used. The IP core is implemented on a Xilinx Virtex-4 FPGA and integrated in a complete video processing platform for a full system realization. In addition to the IP core, bilinear interpolation for image demosaicing with Bayer pattern and an automatic white balance algorithm are implemented for evaluation of the platform. Benchmarking of the hardware implementation has been performed with a total resolution of up to 2048x2048 pixels. Achieved frame rates vary from 25 fps to 345 fps depending on the selected resolution and on the number of used cameras.


    In: ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on, International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2015.
  • Griessl, René; Peykanu, Meysam; Hagemeyer, Jens; Porrmann, Mario; Krupop, Stefan; vor dem Berge, Micha; Kosmann, Lars; Knocke, Patrick; Kierzynka, Michal; Oleksiak, Ariel:
    FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters.
    In: First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputing 2015, 2015. »»
    Fulltext (PDF)

    conference paper / id: 2902039

  • Vohrmann, Marten; Chatterjee, Saikat; Lütkemeier, Sven; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich:
    A 65 nm Standard Cell Library for Ultra Low-power Applications.
    In: 22nd European Conference on Circuit Theory and Design, ECCTD2015, IEEE, 2015. »»

    conference paper / id: 2902041

  • Herbrechtsmeier, Stefan; Jungeblut, Thorsten; Porrmann, Mario:
    Datenflussmodellierung als Methode zur Optimierung von Entwicklungsprozessen am Beispiel der Leiterplattenentwicklung.
    In: Entwurf mechatronischer Systeme, Volume: 343, Wissenschaftsforum Intelligente Technische Systeme, 10. Paderborner Workshop Entwurf mechatronischer Systeme, HNI Verlagsschriftenreihe, 2015. »»

    conference paper / id: 2732431

  • Ragg, Christoph; Jungeblut, Thorsten; Jurke, Benjamin:
    Intelligente Werkzeugmaschinen.
    In: wt Werkstattstechnik online, Volume: 105, Springer VDI-Verlag, 2015. »»
    Fulltext (external)

    article / id: 2752706

  • Damerow, U.; Borzykh, M.; Tabakajew, D.; Schaermann, W.; Hesse, Marc; Homberg, W.; Trächtler, A.; Jungeblut, Thorsten; Michels, J. S.:
    Intelligente Biegeverfahren.
    In: wt Werkstattstechnik online, Volume: 2015, Springer VDI-Verlag, 2015. »»
    Fulltext (external) Abstract

    article / id: 2759093

    Intelligente Biegeverfahren

    Damerow, U.; Borzykh, M.; Tabakajew, D.; Schaermann, W.; Hesse, Marc; Homberg, W.; Trächtler, A.; Jungeblut, Thorsten; Michels, J. S.

    Entwicklung selbstkorrigierender Fertigungsprozesse in der Umformtechnik Ein Schlüssel, die Wirtschaftlichkeit von Biegeverfahren zu steigern, liegt in der Nutzung von Self-X-Technologien. Dabei werden in die heute rein mechanisch gesteuerten Werkzeuge und Maschinen entsprechende Komponenten integriert, welche die kontinuierliche Einhaltung der Soll-Größen sicherstellen. Das Projekt „Self-X-Pro“ des Spitzenclusters „it’s OWL“ zielt auf die Weiterentwicklung von Biegeverfahren zu intelligenten technischen Systemen, die eine Selbstkorrektur realisieren. Intelligent bending processes - Development of self-correcting production processes in forming technology The key to increasing the efficiency of bending processes lies in the use of Self-X-technologies. This is achieved by integration of Self-X-components in purely mechanically driven tools and machinery to ensure continuous compliance of the required nominal values. The project “Self-X-Pro“ within the leading-edge cluster “it’s OWL“ aims at the advancement of bending processes into intelligent engineering systems where self-correction is realized.


    In: wt Werkstattstechnik online, Volume: 2015, Springer VDI-Verlag, 2015.
  • Sievers, Gregor; Daberkow, Julian; Ax, Johannes; Flasskamp, Martin; Kelly, Wayne; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich:
    Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI.
    In: International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) 2015, IEEE, 2015. »»

    conference paper / id: 2760622

  • Ax, Johannes; Sievers, Gregor; Flasskamp, Martin; Kelly, Wayne; Jungeblut, Thorsten; Porrmann, Mario:
    System-Level Analysis of Network Interfaces for Hierarchical MPSoCs.
    In: Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc), International Workshop on Network on Chip Architectures (NoCArc), ACM, 2015. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2783142

    System-Level Analysis of Network Interfaces for Hierarchical MPSoCs

    Ax, Johannes; Sievers, Gregor; Flasskamp, Martin; Kelly, Wayne; Jungeblut, Thorsten; Porrmann, Mario

    Network Interfaces (NIs) are used in Multiprocessor System-on-Chips (MPSoCs) to connect CPUs to a packet switched Network-on-Chip. In this work we introduce a new NI architecture for our hierarchical CoreVA-MPSoC. The CoreVA-MPSoC targets streaming applications in embedded systems. The main contribution of this paper is a system-level analysis of different NI configurations, considering both software and hardware costs for NoC communication. Different configurations of the NI are compared using a benchmark suite of 10 streaming applications. The best performing NI configuration shows an average speedup of 20 for a CoreVA-MPSoC with 32 CPUs compared to a single CPU. Furthermore, we present physical implementation results using a 28 nm FD-SOI standard cell technology. A hierarchical MPSoC with 8 CPU clusters and 4 CPUs in each cluster running at 800 MHz requires an area of 4.56 mm².


    In: Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc), International Workshop on Network on Chip Architectures (NoCArc), ACM, 2015.
2014
  • Tünnermann, Rene; Zehe, Sebastian; Hemminghaus, Jacqueline; Hermann, Thomas:
    Weather to Go - A Blended Sonification Application.
    In: Proceedings of the 20th International Conference on Auditory Display (ICAD2014), Georgia Institute of Technology, 2014. »»
    Abstract

    article / id: 2904603

    Weather to Go - A Blended Sonification Application

    Tünnermann, Rene; Zehe, Sebastian; Hemminghaus, Jacqueline; Hermann, Thomas

    Presented at the 20th International Conference on Auditory Display (ICAD2014), June 22-25, 2014, New York, NY.


    In: Proceedings of the 20th International Conference on Auditory Display (ICAD2014), Georgia Institute of Technology, 2014.
  • Hesse, Marc; Christ, Peter; Hörmann, Timm; Rückert, Ulrich:
    A Respiration Sensor for a Chest-Strap Based Wireless Body Sensor.
    In: SENSORS, 2014 IEEE, 2014. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2730661

    A Respiration Sensor for a Chest-Strap Based Wireless Body Sensor

    Hesse, Marc; Christ, Peter; Hörmann, Timm; Rückert, Ulrich

    In this paper we present a respiration sensor suitable for an integration into a wireless body sensor worn around the chest. The thorax expansion and contraction during in- and exhalation is captured using a force-sensing resistor. Based on the captured thoracic movements, the breaths are determined with a peak detection algorithm. For evaluation, a treadmill experiment with five subjects was conducted using an ergospirometry system as a reference. Overall, an average deviation of -0.32±0.68 min-1 in the respiration rate between the ergospirometry and our sensor was observed. In general, the captured thoracic movements showed breaths as distinctive oscillations, but in some cases a non-optimal pressure transfer between thorax and sensor was observed. Therefore, a mechanical housing mechanism was developed. A comparison of our construction with a respiratory inductance plethysmography (RIP)-based sensor shows a close relationship with the captured thoracic movements during normal and deep respiration.


    In: SENSORS, 2014 IEEE, 2014.
  • Schaermann, W.; Borzykh, M.; Trächtler, A.; Tabakajew, D.; Damerow, U.; Homberg, W.; Hesse, Marc; Jungeblut, Thorsten:
    Selbstkorrigierende Biegeprozesse in der Umformtechnik.
    In: Automation 2014 Smart X - powered by automation, Automation 2014, VDI-Verlag, 2014. »»
    Abstract

    conference paper / id: 2700385

    Selbstkorrigierende Biegeprozesse in der Umformtechnik

    Schaermann, W.; Borzykh, M.; Trächtler, A.; Tabakajew, D.; Damerow, U.; Homberg, W.; Hesse, Marc; Jungeblut, Thorsten

    Die in dieser Veröffentlichung vorgestellten Forschungsergebnisse gründen sich auf dem Innovationsprojekt „Selbstkorrigierende Fertigungsprozesse“, das dem Spitzencluster „Intelligente technische Systeme – it`s OWL“ zugehörig ist. Dieser Beitrag befasst sich im Wesentlichen mit der Analyse und Modellbildung eines Produktionsprozesses im Bereich der Biegeumformung. Mit Hilfe dieser wird es zu einem späteren Zeitpunkt ermöglicht eine selbstkorrigierende Prozessregelung für eine Produktionsanlage zu entwerfen. Das Vorgehen schließt neben der Analyse des bestehenden Prozesses auch die Entwicklung neuartiger Aktorikund Sensorikkonzepte ein. Eine Unterstützung sowohl bei der Analyse als auch der Auslegung bietet hierbei ein neuartiges Simulationsmodell, das vorgestellt wird. Weiterhin findet unter Zuhilfenahme des aufgestellten Modells eine Sensitivitätsanalyse zur Ermittlung von geeigneten Eingriff- und Sensorpositionen statt.


    In: Automation 2014 Smart X - powered by automation, Automation 2014, VDI-Verlag, 2014.
  • Cassano, Luca; Cozzi, Dario; Jungewelter, Dirk; Korf, Sebastian; Hagemeyer, Jens; Porrmann, Mario; Bernadeschi, Cinzia:
    An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems.
    In: DTIS 2014, 9th International conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014. »»

    conference paper / id: 2681362

  • Puttmann, Christoph:
    Ressourceneffiziente Hardware-Software-Kombinationen für Kryptographie mit elliptischen Kurven.
    In: Universität Bielefeld, 2014. »»
    Fulltext (PDF) Abstract

    thesis / id: 2652142

    Ressourceneffiziente Hardware-Software-Kombinationen für Kryptographie mit elliptischen Kurven

    Puttmann, Christoph

    In der heutigen Informationsgesellschaft spielt die sichere Übertragung von elektronischen Daten eine immer wichtigere Rolle. Die hierfür eingesetzten Endgeräte beschränken sich mittlerweile nicht mehr auf klassische, stationäre Computer, sondern es setzen zunehmend mobile Alltagsgegenstände (z.B. Smartphone oder Reisepass) eine sichere Datenübertragung zwingend voraus. Die Anforderungen bezüglich der Ressourcen einer Hardware-Software-Kombination variieren dabei für verschiedene Anwendungsszenarien sehr stark. Kryptographie auf Basis von elliptischen Kurven stellt eine attraktive Alternative zu etablierten asymmetrischen Verfahren dar und wird vermehrt eingesetzt, um sicherheitskritische Daten zu ver- bzw. entschlüsseln sowie deren Integrität und Authentizität sicherzustellen. Im Rahmen dieser Arbeit werden, am Beispiel von Algorithmen für die Kryptographie mit elliptischen Kurven, verschiedene Methoden vorgestellt, um ressourceneffiziente Hardware-Software-Kombinationen zu entwickeln. Es wird eine automatisierte Testumgebung vorgestellt, welche die systematische Entwicklung von ressourceneffizienten Hardware-Software-Kombinationen ermöglicht. Um verschiedene Implementierungen im Hinblick auf ein spezielles Anwendungsszenario miteinander vergleichen zu können, wird eine allgemeine Bewertungsmetrik eingeführt, welche die drei wesentlichen Parameter (Chipfläche, Verlustleistung, Ausführungsdauer) des Entwurfsraumes einer ASIC-Entwicklung berücksichtigt. Basierend auf einer hierarchisch entwickelten, skalierbaren Systemarchitektur wird eine Entwurfsraumexploration für zwei exemplarische Anwendungsszenarien durchgeführt. Mit den angewandten Konzepten der Instruktionssatzerweiterung, der Parallelisierung sowie eines Coprozessor-Ansatzes wird die Ressourceneffizienz auf unterschiedlichen Hierarchieebenen der zugrundeliegenden Systemarchitektur anwendungsspezifisch optimiert. Die Ergebnisse werden mit Hilfe einer FPGA-basierten Entwicklungsumgebung prototypisch evaluiert sowie durch eine ASIC-Realisierung in einer 65-nm-CMOS-Standardzellentechnologie praktisch belegt.


    In: Universität Bielefeld, 2014.
  • Walter, Martin; Ax, Johannes; Buda, Aurel; Nussbaum, K.; Hartfiel, John; Jungeblut, Thorsten; Porrmann, Mario:
    Dynamische Rekonfiguration von Echtzeit-Ethernet-Standards mit harten Echtzeit­anforderungen.
    In: Kommunikation in der Automation – KommA 2014, 2014. »»

    conference paper / id: 2698994

  • Sorrenti, Domenico; Cozzi, Dario; Korf, Sebastian; Cassano, Luca; Hagemeyer, Jens; Porrmann, Mario; Bernadeschi, Cinzia:
    Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems.
    In: 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014. »»

    conference paper / id: 2698999

  • Cozzi, Dario; Jungewelter, Dirk; Kleibrink, Dominik; Korf, Sebastian; Hagemeyer, Jens; Porrmann, Mario; Ilstad, Jorgen:
    AXI-based SpaceFibre IP CORE Implementation.
    In: 6th International SpaceWire Conference, 2014. »»

    conference paper / id: 2699005

  • Seifried, Albert; Trächtler, Ansgar; Kleinjohann, Bernd; Korf, Sebastian; Porrmann, Mario; Heinzemann, Christian; Rasche, Christoph; Sondermann-Woelke, Christoph; Priesterjahn, Claudia; Steenken, Dominik; Rammig, Franz-Josef; Wehrheim, Heike; Kessler, Jan Henning; Gausemeier, Jürgen; Stahl, Katharina; Flasskamp, Kathrin; Witting, Katrin; Kleinjohann, Lisa; Krüger, Martin; Dellnitz, Michael; Iwanek, Peter; Reinold, Peter; Hartmann, Philip; Dorociak, Rafal; Timmermann, Robert; Ober-Blöbaum, Sina; Groesbrink, Stefan; Ziegert, Steffen; Xie, Tao; Meyer, Tobias; Sextro, Walter; Schäfer, Wilhelm; Müller, Wolfgang; Zhao, Yuhong; Gausemeier, Jürgen; Rammig, Franz Josef; Schäfer, Wilhelm; Sextro, Walter:
    Methods of Improving the Dependability of Self-optimizing Systems.
    In: Dependability of Self-Optimizing Mechatronic Systems, Springer Verlag, 2014. »»
    Abstract

    book chapter / id: 2732260

    Methods of Improving the Dependability of Self-optimizing Systems

    Seifried, Albert; Trächtler, Ansgar; Kleinjohann, Bernd; Korf, Sebastian; Porrmann, Mario; Heinzemann, Christian; Rasche, Christoph; Sondermann-Woelke, Christoph; Priesterjahn, Claudia; Steenken, Dominik; Rammig, Franz-Josef; Wehrheim, Heike; Kessler, Jan Henning; Gausemeier, Jürgen; Stahl, Katharina; Flasskamp, Kathrin; Witting, Katrin; Kleinjohann, Lisa; Krüger, Martin; Dellnitz, Michael; Iwanek, Peter; Reinold, Peter; Hartmann, Philip; Dorociak, Rafal; Timmermann, Robert; Ober-Blöbaum, Sina; Groesbrink, Stefan; Ziegert, Steffen; Xie, Tao; Meyer, Tobias; Sextro, Walter; Schäfer, Wilhelm; Müller, Wolfgang; Zhao, Yuhong

    Various methods have been developed in the Collaborative Research Center 614 which can be used to improve the dependability of self-optimizing systems. These methods are presented in this chapter. They are sorted into two categories with regard to the development process of self-optimizing systems. On one hand, there are methods which can be applied during the Conceptual Design Phase. On the other hand, there are methods that are applicable during Design and Development. There are domain-spanning methods as well as methods that have been specifically developed for particular domains, e.g., software engineering or control engineering. The methods address different attributes of dependability, such as reliability, availability or safety. Each section is prefaced with a short overview of the classification of the described method regarding the corresponding domain(s), as well as its dependability attributes, to provide the reader with a brief outline of the methods’ areas of application. Information about independently applicable methods or existing relationships and interactions with other methods or third-party literature is also provided. The development process for self-optimizing mechatronic systems which was introduced in Chap. 2 consists of two main phases: Conceptual Design and Design and Development. The main result of the Conceptual Design is the Principle Solution, which includes all information required for the concrete development during the second phase.


    In: Dependability of Self-Optimizing Mechatronic Systems, Springer Verlag, 2014.
  • Gausemeier, Jürgen; Korf, Sebastian; Porrmann, Mario; Stahl, Katharina; Sudmann, Oliver; Vaßholz, Mareen; Gausemeier, Jürgen; Rammig, Franz Josef; Schäfer, Wilhelm:
    Development of Self-Optimizing Systems.
    In: Design Methodology for Intelligent Technical Systems – Develop Intelligent Technical Systems of the Future, Springer Verlag, 2014. »»
    Abstract

    book chapter / id: 2732400

    Development of Self-Optimizing Systems

    Gausemeier, Jürgen; Korf, Sebastian; Porrmann, Mario; Stahl, Katharina; Sudmann, Oliver; Vaßholz, Mareen

    In the development of self-optimizing systems, developers have to face different challenges, such as the multidisciplinarity of mechatronics, cross-linking between the subsystems, the lack of current knowledge in the fields of advanced mathematics and artificial intelligence, and increased dependability requirements. To support the developer in this challenging task adequately, the Collaborative Research Center 614 has developed a design methodology consisting of a reference process, methods and tools. The reference process is divided into two phases: the ”Domain-Spanning Conceptual Design” and the ”Domain-Specific Design and Development”. In the first phase, the domain-spanning model-based aproach CONSENS (CONceptual design Specification technique for the ENgineering of complex Systems) is used to create a common understanding basis between the different domains involved. Based on the Principle Solution developed in this phase, the ”Domain-Specific Design and Development” is planned and implemented. To ensure the development of dependable self-optimizing systems, domain-spanning and domain-specific dependability engineering methods can be used. The developer encounters a significant number of these methods, that have to be integrated into the process to obtain an individualized development process for the specific development task.


    In: Design Methodology for Intelligent Technical Systems – Develop Intelligent Technical Systems of the Future, Springer Verlag, 2014.
  • Kelly, Wayne; Flasskamp, Martin; Sievers, Gregor; Ax, Johannes; Chen, Jianing; Klarhorst, Christian; Ragg, Christoph; Jungeblut, Thorsten; Sorensen, Andrew:
    A Communication Model and Partitioning Algorithm for Streaming Applications for an Embedded MPSoC.
    In: International Symposium on System-on-Chip (SoC), IEEE, 2014. »»
    Fulltext (external) Abstract

    conference paper / id: 2753235

    A Communication Model and Partitioning Algorithm for Streaming Applications for an Embedded MPSoC

    Kelly, Wayne; Flasskamp, Martin; Sievers, Gregor; Ax, Johannes; Chen, Jianing; Klarhorst, Christian; Ragg, Christoph; Jungeblut, Thorsten; Sorensen, Andrew

    Energy efficient embedded computing enables new application scenarios in mobile devices like software-defined radio and video processing. The hierarchical multiprocessor considered in this work may contain dozens or hundreds of resource efficient VLIW CPUs. Programming this number of CPU cores is a complex task requiring compiler support. The stream programming paradigm provides beneficial properties that help to support automatic partitioning. This work describes a compiler for streaming applications targeting the self-build hierarchical CoreVA-MPSoC multiprocessor platform. The compiler is supported by a programming model that is tailored to fit the streaming programming paradigm. We present a novel simulated-annealing (SA) based partitioning algorithm, called Smart SA. The overall speedup of Smart SA is 12.84 for an MPSoC with 16 CPU cores compared to a single CPU implementation. Comparison with a state of the art partitioning algorithm shows an average performance improvement of 34.07%.


    In: International Symposium on System-on-Chip (SoC), IEEE, 2014.
  • Sabena, Davide; Sterpone, Luca; Schölzel, M.; Koal, T.; Vierhaus, H.T.; Wong, S.; Glein, R.; Rittner, F.; Stender, C.; Porrmann, Mario; Hagemeyer, Jens:
    Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications.
    In: Proceedings of 19th IEEE European Test Symposium (ETS), 2014. »»
    Fulltext (external) Abstract

    conference paper / id: 2681323

    Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications

    Sabena, Davide; Sterpone, Luca; Schölzel, M.; Koal, T.; Vierhaus, H.T.; Wong, S.; Glein, R.; Rittner, F.; Stender, C.; Porrmann, Mario; Hagemeyer, Jens

    Reconfigurable architectures are increasingly employed in a large range of embedded applications, mainly due to their ability to provide high performance and high flexibility, combined with the possibility to be tuned according to the specific task they address. Reconfigurable systems are today used in several application areas, and are also suitable for systems employed in safety-critical environments. The actual development trend in this area is focused on the usage of the reconfigurable features to improve the fault tolerance and the self-test and the self-repair capabilities of the considered systems. The state-of-the-art of the reconfigurable systems is today represented by Very Long Instruction Word (VLIW) processors and reconfigurable systems based on partially reconfigurable SRAM-based FPGAs. In this paper, we present an overview and accurate analysis of these two type of reconfigurable systems. The content of the paper is focused on analyzing design features, fail-safe and reconfigurable features oriented to self-adaptive mitigation and redundancy approaches applied during the design phase. Experimental results reporting a clear status of the test data and fault tolerance robustness are detailed and commented


    In: Proceedings of 19th IEEE European Test Symposium (ETS), 2014.
  • Hübener, Boris; Sievers, Gregor; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich:
    CoreVA: A Configurable Resource-efficient VLIW Processor Architecture.
    In: Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014, IEEE, 2014. »»

    conference paper / id: 2698929

  • Christ, Peter; Rückert, Ulrich; Fernandez-Chimeno, Mireya; Fernandes, Pedro L.; Alvarez, Sergio; Stacey, Deborah; Solé-Casals, Jordi; Fred, Ana; Gamboa, Hugo:
    Identification of Athletes During Walking and Jogging Based on Gait and Electrocardiographic Patterns.
    In: Biomedical Engineering Systems and Technologies, Volume: 452,, Springer Berlin Heidelberg, 2014. »»
    Fulltext (external)

    book chapter / id: 2704390

  • Griessl, René; Peykanu, Meysam; Hagemeyer, Jens; Porrmann, Mario; Krupop, Stefan; Vor dem Berge, Michael; Kiesel, Thomas; Christmann, Wolfgang:
    A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters.
    In: Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014, IEEE, 2014. »»

    conference paper / id: 2698930

  • Irwansyah, Arif; Ibraheem, Omar Waleed; Klimeck, Daniel; Porrmann, Mario; Rückert, Ulrich:
    FPGA-based Generic Architecture for Rapid Prototyping of Video Hardware Accelerators using NoC AXI4-Stream Interconnect and GigE Vision Camera Interfaces.
    In: Bildverarbeitung in der Automation (BVAu) 2014, 2014. »»

    conference paper / id: 2698992

2013
  • Lachmair, Jan; Merényi, E.; Porrmann, Mario; Rückert, Ulrich:
    A reconfigurable neuroprocessor for self-organizing feature maps.
    In: Neurocomputing, Volume: 112, Elsevier BV, 2013. »»
    Fulltext (external) Abstract

    article / id: 2575531

    A reconfigurable neuroprocessor for self-organizing feature maps

    Lachmair, Jan; Merényi, E.; Porrmann, Mario; Rückert, Ulrich

    In this article we compare a scalable FPGA-based hardware accelerator for the emulation of Self-Organizing Feature Maps (SOMs) with a multi-threaded software implementation on a state-of-the-art multi-core microprocessor. After discussing the mapping of SOMs to the reconfigurable digital hardware implementation, we present how the modular system architecture can be flexibly adapted to various application datasets as well as to variants of SOMs like Conscience SOM. Hyperspectral image processing is used as a benchmark scenario for the comparison of our FPGA-based hardware accelerator and state-of-the-art multi-core microprocessors. The hardware costs, power consumption, and scalability of the FPGA based accelerator using Xilinx Virtex-4 FPGAs are discussed. For the real-world datasets used here, which require large SOMs, a speedup and energy reduction of one order of magnitude is achieved.


    In: Neurocomputing, Volume: 112, Elsevier BV, 2013.
  • Walter, Oliver; Korthals, Timo; Haeb-Umbach, Reinhold; Raj, Bhiksha:
    A hierarchical system for word discovery exploiting DTW-based initialization.
    In: IEEE Workshop on Automatic Speech Recognition and Understanding (ASRU), 2013, ASRU 2013, IEEE, 2013. »»
    Fulltext (external) Abstract

    conference paper / id: 2902861

    A hierarchical system for word discovery exploiting DTW-based initialization

    Walter, Oliver; Korthals, Timo; Haeb-Umbach, Reinhold; Raj, Bhiksha

    Discovering the linguistic structure of a language solely from spoken input asks for two steps: phonetic and lexical discovery. The first is concerned with identifying the categorical subword unit inventory and relating it to the underlying acoustics, while the second aims at discovering words as repeated patterns of subword units. The hierarchical approach presented here accounts for classification errors in the first stage by modelling the pronunciation of a word in terms of subword units probabilistically: a hidden Markov model with discrete emission probabilities, emitting the observed subword unit sequences. We describe how the system can be learned in a completely unsupervised fashion from spoken input. To improve the initialization of the training of the word pronunciations, the output of a dynamic time warping based acoustic pattern discovery system is used, as it is able to discover similar temporal sequences in the input data. This improved initialization, using only weak supervision, has led to a 40% reduction in word error rate on a digit recognition task.


    In: IEEE Workshop on Automatic Speech Recognition and Understanding (ASRU), 2013, ASRU 2013, IEEE, 2013.
  • Korf, Sebastian; Sievers, Gregor; Ax, Johannes; Cozzi, Dario; Jungeblut, Thorsten; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich:
    Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme.
    In: Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme, 2013. »»
    Fulltext (PDF)

    conference paper / id: 2576115

  • Jungeblut, Thorsten; Hübener, Boris; Porrmann, Mario; Rückert, Ulrich:
    A Systematic Approach for Optimized Bypass Configurations for Application-specific Embedded Processors.
    In: ACM Trans. Embed. Comput. Syst., Volume: 13, Association for Computing Machinery (ACM), 2013. »»
    Fulltext (external)

    article / id: 2634614

  • Sterpone, Luca; Porrmann, Mario; Hagemeyer, Jens:
    A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing.
    In: IEEE Transactions on Computers, Volume: 62, Institute of Electrical & Electronics Engineers (IEEE), 2013. »»
    Abstract

    article / id: 2622226

    A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing

    Sterpone, Luca; Porrmann, Mario; Hagemeyer, Jens

    Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance optimization, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. The developed systems have been enabled to space harsh environments thanks to an analytical analysis of the radiation effects on its most critical reconfigurable components. Aiming at that scope, a new algorithm for the analysis of critical radiation effects, in particular, related to Single Event Upsets (SEUs) and Multiple Event Upsets (MEUs) has been developed to obtain an effective estimation of the radiation impact and enabling the tuning of the component mapping reducing the routing interaction between the reconfigurable placed modules in their different feasible positions. The experimental performance of the system has been evaluated by a proper dynamic reconfiguration scenario, demonstrating a partial reconfiguration at 400 MByte/s, blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. The fault tolerance capability has been proven by means of a new analysis algorithm and by fault injection campaigns of SEUs and MCUs into the FPGA configuration memory.


    In: IEEE Transactions on Computers, Volume: 62, Institute of Electrical & Electronics Engineers (IEEE), 2013.
  • Tanoto, Andry; Gomez, Javier V.; Mavridis, Nikolaos; Li, Hanyi; Rückert, Ulrich; Garrido, Santiago:
    Teletesting: Remote Path Planning Experimentation and Benchmarking in the TeleWorkbench.
    In: IEEE European Conference on Mobile Robots (ECMR'13), 2013. »»
    Fulltext (external)

    conference paper / id: 2634404

  • Christ, Peter; Sievers, Gregor; Einhaus, Julian; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich:
    Pareto-optimal Signal Processing on Low-Power Microprocessors.
    In: Proceedings of the 12th IEEE International Conference on SENSORS, 2013. »»
    Fulltext (external)

    conference paper / id: 2634649

  • Sievers, Gregor; Christ, Peter; Einhaus, Julian; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich:
    Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing Applications.
    In: 2013 NORCHIP, NORCHIP, 2013. »»

    conference paper / id: 2637667

  • Christ, Peter; Werner, F.; Rückert, Ulrich; Mielebacher, J.; Alvarez, Sergio; Solé-Casals, Jordi; Fred, Ana; Gamboa, Hugo:
    Athlete Identification using Acceleration and Electrocardiographic Measurements Recorded with a Wireless Body Sensor.
    In: Proc. of the 6th Int. Conf. on Bio-Inspired Systems and Signal Processing, Int. Joint Conf. on Biomedical Engineering Systems and Technologies, SciTePress, 2013. »»
    Fulltext (PDF) Fulltext (external)

    conference paper / id: 2576303

  • Lütkemeier, Sven; Jungeblut, Thorsten; Berge, Hans Kristian Otnes; Aunet, Snorre; Porrmann, Mario; Rückert, Ulrich:
    A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control.
    In: IEEE Journal Of Solid-State Circuits, Volume: 48, Institute of Electrical & Electronics Engineers (IEEE), 2013. »»
    Abstract

    article / id: 2560236

    A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control

    Lütkemeier, Sven; Jungeblut, Thorsten; Berge, Hans Kristian Otnes; Aunet, Snorre; Porrmann, Mario; Rückert, Ulrich

    An energy-efficient SoC with 32 b subthreshold RISC processor cores, 32 kB conventional cache memory, and 9T ultra-low voltage (ULV) SRAM based on a flexible and extensible architecture was fabricated on a 2.7 mm(2) test chip in 65 nm low power CMOS. The processor cores are based on a custom standard cell library that was designed using a multiobjective approach to optimize noise margins, switching energy, and propagation delay simultaneously. The cores operate over a supply voltage range from 200 mV (best samples) to 1.2 V with clock frequencies from 10 kHz to 94 MHz at room temperature. The lowest energy consumption per cycle of 9.94 pJ is observed at 325 mV and 133 kHz. A 2 kb ULV SRAM macro achieves minimum energy per operation at averages of 321 mV (0.030 sigma/mu), 567 fJ (0.037 sigma/mu), and 730 kHz (0.184 sigma/mu), for equal number of 32 b read/write operations. The off-chip performance and power management subsystem provides dynamic voltage and frequency scaling (DVFS) combined with an adaptive supply voltage generation for dynamic PVT compensation.


    In: IEEE Journal Of Solid-State Circuits, Volume: 48, Institute of Electrical & Electronics Engineers (IEEE), 2013.
  • Desogus, Marco; Sterpone, Luca; Porrmann, Mario; Hagemeyer, Jens; Illstad, Jorgen:
    Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience.
    In: RADECS proceedings, Volume: 2, IEEE / Institute of Electrical and Electronics Engineers, 2013. »»
    Fulltext (external) Abstract

    conference paper / id: 2681289

    Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience

    Desogus, Marco; Sterpone, Luca; Porrmann, Mario; Hagemeyer, Jens; Illstad, Jorgen

    In this paper we describe the hardening of a Dynamically Reconfigurable Processing Module (DRPM) Systems implemented on modern SRAM-based FPGAs. We also report the neutron radiation testing campaigns when the system is implemented on Xilinx Virtex-4 and Virtex-5 SRAM-based FPGAs. Experimental results demonstrate the effectives of the proposed method


    In: RADECS proceedings, Volume: 2, IEEE / Institute of Electrical and Electronics Engineers, 2013.
  • Sterpone, Luca; Sabena, D.; Ullah, A.; Porrmann, Mario; Hagemeyer, Jens; Ilstad, Jorgen:
    Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.
    In: Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on, 2013. »»
    Fulltext (external) Abstract

    conference paper / id: 2681304

    Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture

    Sterpone, Luca; Sabena, D.; Ullah, A.; Porrmann, Mario; Hagemeyer, Jens; Ilstad, Jorgen

    The usage of reconfigurable systems is of increasingly interest for space and avionic applications. In the present work we propose an implementation flow for hardening Dynamically Reconfigurable Processing Module (DRPM) Systems implemented on modern SRAM-based FPGAs. We also report neutron radiation testing campaigns when the system is implemented on Xilinx Virtex-4 and Virtex-5 SRAM-based FPGAs. Experimental results performed by heavy-ions radiation experiments and fault injection campaigns demonstrate the effectiveness of the proposed method.


    In: Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on, 2013.
  • Cassano, Luca; Cozzi, Dario; Korf, Sebastian; Hagemeyer, Jens; Porrmann, Mario; Sterpone, Luca:
    On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems.
    In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, DATE 2013 Design Automation & Test in Europe, IEEE, 2013. »»

    conference paper / id: 2576042

2012
  • Hagemeyer, Jens; Hilgenstein, Arne; Jungewelter, Dirk; Cozzi, Dario; Felicetti, Carmelo; Rückert, Ulrich; Korf, Sebastian; Köster, Markus; Margaglia, Fabio; Porrmann, Mario; Dittmann, Florian; Ditze, Michael; Harris, Julian; Sterpone, Luca; Ilstad, Jorgen:
    A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing.
    In: Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems, Volume: (AHS-2012), NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012), 2012. »»
    Fulltext (external)

    conference paper / id: 2517354

  • Durelli, G.; Santambrogio, M.D.; Cresci, F.; Porrmann, Mario; Sciuto, D.:
    Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling..
    In: 19th Reconfigurable Architectures Workshop (RAW 2012), 2012. »»
    Fulltext (external)

    conference paper / id: 2493814

  • Rückert, Ulrich; Merenyi, Erzsebet:
    Parallel Neural Hardware: The Time is Right.
    In: ESANN 2012 proceedings, European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning. Bruges (Belgium), 25-27 April 2012, 2012. »»
    Fulltext (external)

    conference paper / id: 2547438

  • Al-Bermani, Ali; Wördehoff, Christian; Jan, Omar H. A.; Puntsri, Kidsanapong; Rückert, Ulrich; Noé, Reinhold:
    Real-time Comparison of Blind Phase Search with Different Angle Resolutions for 16-QAM.
    In: IEEE Photonics 2012 Conference (IPC12 - formerly LEOS), 23-27 September 2012, 2012. »»

    conference paper / id: 2549895

  • Al-Bermani, A.; Wördehoff, Christian; Puntsri, K.; Omar, J.; Rückert, Ulrich; Noe, R.:
    Real-time synchronous 16-QAM Optical Transmission system Using Blind Phase Search and QPSK Partitioning Carrier Recovery Techniques.
    In: Photonische Netze - 13. ITG-Fachtagung 07.05.2012 - 08.05.2012 in Leipzig, Germany, 2012. »»
    Fulltext (external)

    conference paper / id: 2547432

  • Zehe, Sebastian; Großhauser, Tobias; Hermann, Thomas:
    BRIX - An Easy-to-Use Modular Sensor and Actuator Prototyping Toolkit.
    In: Tenth Annual IEEE International Conference on Pervasive Computing and Communications, Workshop Proceedings, 4th International Workshop on Sensor Networks and Ambient Intelligence (SeNAmI 2012), IEEE, 2012. »»

    BRIX - An Easy-to-Use Modular Sensor and Actuator Prototyping Toolkit

    Zehe, Sebastian; Großhauser, Tobias; Hermann, Thomas

    In this paper we present BRIX, a novel modular hardware prototyping platform for applications in mobile, wearable and stationary sensing, data streaming and feedback. The system consists of three different types of compact stack- able modules, which can adapt to various applications and scenarios. The core of BRIX is a base module that contains basic motion sensors, a processor and a wireless interface. A battery module provides power for the system and makes it a mobile device. Different types of extension modules can be stacked onto the base module to extend its scope of functions by sensors, actuators and interactive elements. BRIX allows a very intuitive, inexpensive and expeditious prototyping that does not require knowledge in electronics or hardware design. In an example application, we demonstrate how BRIX can be used to track human body movements.


    In: Tenth Annual IEEE International Conference on Pervasive Computing and Communications, Workshop Proceedings, 4th International Workshop on Sensor Networks and Ambient Intelligence (SeNAmI 2012), IEEE, 2012.
  • Lütkemeier, Sven; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich:
    A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage Control.
    In: Proc. of the International Solid-State Circuits Conference (ISSCC), 2012. »»
    Abstract

    conference paper / id: 2475063

    A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage Control

    Lütkemeier, Sven; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich

    We present an energy efficient 32-bit microcontroller operating from 200 mV to 1.2 V with clock frequencies ranging from 10 kHz to 100 MHz at 25°C. The minimum energy per cycle of 9.94 pJ occurs at 325 mV and 133 kHz. An adaptive supply voltage control based on a PLL is proposed for the compensation of process and temperature variation, aiming at constant frequency operation.


    In: Proc. of the International Solid-State Circuits Conference (ISSCC), 2012.
  • Jungeblut, Thorsten; Ax, Johannes; Porrmann, Mario; Rückert, Ulrich:
    A TCMS-based architecture for GALS NoCs..
    In: 2012 IEEE International Symposium on Circuits and Systems, 2012. »»
    Abstract

    conference paper / id: 2493813

    A TCMS-based architecture for GALS NoCs.

    Jungeblut, Thorsten; Ax, Johannes; Porrmann, Mario; Rückert, Ulrich

    We propose a TCMS based architecture of GALS NoCs based on the GigaNoC approach, a scalable NoC featuring packet-switched wormhole routing. At a clock frequency of 750 MHz a link bandwidth of up to 6 GByte/s is achieved. The resource efficiency of mesochronous and asynchronous communication links is analyzed. The asynchronous coupling of the PE to the switch boxes is evaluated. This allows for multi-voltage/multi-frequency scenarios, where the performance of each PE is adapted to the current performance requirements. TCMS-based communication links and asynchronously coupled PEs allow for the high efficiency of GALS-based NoCs with moderate additional resource requirements.


    In: 2012 IEEE International Symposium on Circuits and Systems, 2012.
  • Backhaus, Andreas; Lachmair, Jan; Rückert, Ulrich; Seiffert, Udo:
    Hardware accelerated real time classification of hyperspectral imaging data for coffee sorting.
    In: European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, Esann 2012, 2012. »»
    Fulltext (external)

    conference paper / id: 2575545

  • Tanoto, Andry; Li, Hanyi; Rückert, Ulrich; Sitte, Joaquin:
    Scalable and Flexible Vision-Based Multi-Robot Tracking System.
    In: Proceedings of the IEEE International Symposium on Intelligent Control (ISIC), Multi-Conference on Systems and Control, IEEE, 2012. »»

    conference paper / id: 2546464

  • Tanoto, Andry; Rückert, Ulrich:
    Local Navigation Strategies for Multi-Robot Exploration: From Simulation to Experimentation with Mini-Robots.
    In: Procedia Engineering, Volume: 41, International Symposium on Robotics and Intelligent Sensors (IRIS 2012), Elsevier, 2012. »»

    conference paper / id: 2547051

  • Rückert, Ulrich; Sitte, Joaquin; Werner, Felix:
    Advances in Autonomous Mini Robots: Proceedings of the 6-th AMiRE Symposium.
    In: AMiRE, Springer, 2012. »»

    conference publication / id: 2493982

  • Romoth, J.; Jungewelter, Dirk; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich:
    Optimizing inter-FPGA communication by automatic channel adaptation.
    In: Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on, 2012. »»
    Abstract

    conference paper / id: 2559365

    Optimizing inter-FPGA communication by automatic channel adaptation

    Romoth, J.; Jungewelter, Dirk; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich

    Tightly coupled multi-FPGA architectures gain more and more interest in various application areas, like prototyping MPSoC, code breaking, or artificial neural networks, just to name a few. Communication protocols and implementations have to deal with rising clock frequencies on the one hand and short time to market demands on the other hand. These tight schedules and limited routing areas often lead to PCB routing which is not ideal in terms of length matching and therefore introduces different delays in parallel transmission lines. Crosstalk, impedance mismatch, and jitter further deteriorate the quality of the received signal. In order to achieve optimum data rates modern FPGAs offer different mechanisms to adapt to the behavior of the channel. This paper introduces a communication protocol and an architecture which evaluates the channel delays and automatically generates the configuration for the different mechanisms offered by the used FPGAs. The protocol supports several transmission standards and can be scaled to different physical and virtual channel widths.


    In: Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on, 2012.
  • Al-Bermani, Ali; Wördehoff, Christian; Puntsri, Kidsanapong; Jan, Omar H.A.; Rückert, Ulrich; Noé, Reinhold:
    Phase Estimation Filter Length Tolerance for Real-Time 16-QAM Transmission System Using QPSK Partitioning.
    In: Workshop der ITG-Fachgruppe 5.3.1, 5-6. July 2012, Gewerkschaftshaus Nürnberg, 2012. »»
    Fulltext (PDF)

    conference paper / id: 2549880

  • Lachmair, Jan; Merenyi, E.; Porrmann, Mario; Rückert, Ulrich:
    gNBXe - a Reconfigurable Neuroprocessor for Various Types of Self-Organizing Maps.
    In: European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2012, 2012. »»
    Fulltext (external)

    conference paper / id: 2493811

  • Herbrechtsmeier, Stefan; Rückert, Ulrich; Sitte, Joaquin; Rückert, Ulrich; Sitte, Joaquin; Werner, Felix:
    AMiRo – Autonomous Mini Robot for Research and Education.
    In: Advances in Autonomous Mini Robots, AMiRE, Springer, 2012. »»
    Abstract

    conference paper / id: 2493986

    AMiRo – Autonomous Mini Robot for Research and Education

    Herbrechtsmeier, Stefan; Rückert, Ulrich; Sitte, Joaquin

    This paper describes the motivation, system architecture and design details of a mini robot for research and education. The main objective is to produce a set of electronic modules for sensor processing, actuator control and cognitive processing that fully utilise currently available electronics technology for the construction of mini robots capable of rich autonomous behaviours. These modules are used for the two wheeled AMiRo mini robot that meets the size requirements for participation in the AMiRESoT robot soccer league. All mechanical parts for the robot are off-the-shelf components or can be fabricated with common drilling, turning and milling machines. The connection between the modules is well defined and supports standard interfaces from parallel camera capture interfaces down to simple serial interfaces.


    In: Advances in Autonomous Mini Robots, AMiRE, Springer, 2012.
  • Tanoto, Andry; Werner, Felix; Rückert, Ulrich; Rückert, Ulrich; Sitte, Joaquin; Werner, Felix:
    Multi-Robot System Validation: From Simulation to Prototyping with Minirobots in the Teleworkbench.
    In: Advances in Autonomous Mini Robots, AMiRE, Springer, 2012. »»
    Abstract

    conference paper / id: 2493993

    Multi-Robot System Validation: From Simulation to Prototyping with Minirobots in the Teleworkbench

    Tanoto, Andry; Werner, Felix; Rückert, Ulrich

    One challenging aspect in the development of multi-robot systems is their validation in a real environment. However, experiments with real robots are considerably tedious as experimenting is repetitive and consists of several steps: setup, execution, data logging, monitoring, and analysis. Moreover, experiments also require many resources especially in the case when involving many robots. This paper describes the role of the Teleworkbench as a platform for conducting experiments involving mini robots. The Teleworkbench offers functionality that can help users in validating their robot software from simulation to prototyping using mini robots. A traffic management system is used as a scenario for demonstrating the support of the Teleworkbench for validating multi-robot systems.


    In: Advances in Autonomous Mini Robots, AMiRE, Springer, 2012.
2011
  • Christ, Peter; Neuwinger, Bernd; Werner, Felix; Rückert, Ulrich:
    Performance Analysis of the nRF24L01 Ultra-Low-Power Transceiver in a Multi-Transmitter and Multi-Receiver Scenario.
    In: 2011 IEEE sensors proceedings, IEEE Sensors, IEEE, 2011. »»
    Abstract

    conference paper / id: 2300464

    Performance Analysis of the nRF24L01 Ultra-Low-Power Transceiver in a Multi-Transmitter and Multi-Receiver Scenario

    Christ, Peter; Neuwinger, Bernd; Werner, Felix; Rückert, Ulrich

    Low-power Wireless Sensor Networks (WSN) are used in various energy constraint applications in industry, medicine, and human motion monitoring. In this paper we analyze the transmission performance of a WSN in a static indoor test setup consisting of 5 to 14 transmitters and up to four receivers. In particular, we consider the nRF24L01 transceiver that implements the proprietary ANT protocol and operates in the 2.4 GHz ISM band. We conduct tests in over 500 configurations with different message frequencies, packet sizes and number of transmitters. Our tests experimentally point out the trade-off between rate and package length regarding the number of lost packets. Moreover, we show that using multiple receivers reduces the amount of consecutively lost packages. The obtained results provide valuable insights for drawing conclusions for an application specific device configuration as well as redundancy mechanisms for maximizing the information throughput.


    In: 2011 IEEE sensors proceedings, IEEE Sensors, IEEE, 2011.
  • Jungeblut, Thorsten:
    Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren.
    In: Universität Bielefeld, 2011. »»
    Fulltext (PDF) Abstract

    thesis / id: 2407551

    Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren

    Jungeblut, Thorsten

    Die zunehmende Miniaturisierung digitaler Schaltkreise durch moderne Fertigungsverfahren und die damit verbundene steigende Integrationsdichte von mikroelektronischen Schaltkreisen erlaubt die Realisierung von immer komplexeren und leistungsfähigeren Prozessoren. Die Steigerung der Performanz durch eine reine Erhöhung der Taktfrequenz wirkt sich jedoch nachteilig auf die Leistungsaufnahme des Systems aus. Neue Architekturen stellen die geforderte Leistungsfähigkeit durch eine höhere Parallelität zur Verfügung. Diese ermöglicht eine höhere Energieeffizienz, da die Taktfrequenz eines Parallelprozessors vergleichsweise niedrig gehalten werden kann. Es gilt, eine hohe Ressourceneffizienz, d.h. einen guten Kompromiss zwischen Performanz und Bedarf an Ressourcen, wie Fläche oder Leistungsaufnahme, zu erreichen. Die eng gekoppelten Funktionseinheiten skalierbarer Very-Long-Instruction-Word (VLIW)-Prozessoren eignen sich insbesondere für Anwendungsszenarien, in denen eine hohe Ressourceneffizienz gefordert ist. Diese Arbeit dokumentiert die Entwurfsraumexploration einer skalierbaren und ressourceneffizienten VLIW-Architektur – dem CoreVA-Prozessor. Als Grundlage der Entwicklung dient ein, in Kooperation mit der Fachgruppe "Programmiersprachen und Übersetzer" der Universität Paderborn entwickelter, dualer Entwurfsablauf, der auf einer zentralen Prozessorspezifikation basiert. Der hohe Automatismus dieses Entwurfsablaufs ermöglicht kürzere Iterationszyklen während der Entwicklung und somit die Abdeckung größerer Entwurfsräume, als es bisher möglich war. Ziel der Entwicklung war die Implementierung und Realisierung einer anwendungsspezifischen Architektur, die möglichst gut an das jeweilige Anwendungsszenario angepasst ist. Die Nutzbarkeit des in dieser Arbeit entwickelten Entwurfsablaufes wird anhand der Entwurfsraumexploration des CoreVA-Prozessors gezeigt. Neben der Exploration der funktionalen Parallelität des Prozessorkerns wird auch eine Analyse der Forwarding-Architektur und des Speicher-Subsystems vorgestellt. Zur weiteren Steigerung der Ressourceneffizienz können Hardware-Beschleuniger an das CoreVA-System gekoppelt werden. Verschiedene Anbindungsvarianten erlauben sowohl die eng gekoppelte Integration direkt an den Prozessorkern als auch die flexible Anbindung von externen Hardware-Erweiterungen auf einem dedizierten rekonfigurierbaren Baustein. Die Vorstellung der prototypischen Implementierungen sowohl als FPGA-Prototyp als auch als ASIC-Realisierung bildet den Abschluss dieser Dissertation. In einer 65 nm Low-Power-Standardzellentechnologie von STMicroelectronics belegt der vierfach parallele CoreVA-Prozessor eine Chipfläche von 2,7 mm². Bei einer Taktfrequenz von 400 MHz liefert die Architektur einen Durchsatz von bis zu 3,2 Milliarden Operationen pro Sekunde. Die Leistungsaufnahme liegt bei durchschnittlich 169 mW. Damit wird die Ressourceneffizienz der entwickelten skalierbaren VLIW-Architektur deutlich.


    In: Universität Bielefeld, 2011.
  • Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Rückert, Ulrich; Noé, Reinhold:
    Nonlinear Effect of IQ Modulator in a Realtime Synchronous 16-QAM Transmission System.
    In: IEEE Photonics 2011 (IPC11), formerly (LEOS), IEEE, 2011. »»
    Abstract

    conference paper / id: 2406697

    Nonlinear Effect of IQ Modulator in a Realtime Synchronous 16-QAM Transmission System

    Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Rückert, Ulrich; Noé, Reinhold

    Different operation points of a 16-QAM modulator are tested in realtime. An optimal condition is found which minimizes BER. The FEC threshold was reached for a receiver input power below -30 dBm.


    In: IEEE Photonics 2011 (IPC11), formerly (LEOS), IEEE, 2011.
  • Jungeblut, Thorsten; Liß, Christian; Porrmann, Mario; Rückert, Ulrich; Zorba, N.; Skianis, C.; Verikoukis, C.:
    Design-space Exploration for Flexible WLAN Hardware.
    In: Cross Layer Designs in WLAN Systems, Troubador Publishing, 2011. »»

    book chapter / id: 2018536

  • Christ, Peter; Werner, Felix; Rückert, Ulrich; Mielebacher, Jörg; Morrison, B.; Hamza, M. H.:
    An approach for determining linear velocities of athletes from acceleration measurements using a neural network.
    In: Proc. of the 6th IASTED Int. Conf. on Biomechanics, ACTA Press, 2011. »»
    Abstract

    conference paper / id: 2372545

    An approach for determining linear velocities of athletes from acceleration measurements using a neural network

    Christ, Peter; Werner, Felix; Rückert, Ulrich; Mielebacher, Jörg

    Abstract: "With recent technology advancements, miniaturized wireless body sensor (WBS) systems equipped with accelerometers allow the recording of an athlete’s actions without impact on their execution. This paper addresses the problem of determining linear velocities of athletes using a single tri-axial accelerometer located in a WBS on a chest strap. We propose using a neural network to associate features extracted from acceleration signals in time and frequency domain with particular velocities. This method neither requires a kinematic model nor information on characteristics of an athlete (e.g. height or weight). In a treadmill experiment with 20 subjects we obtain more than 97% correct classifications for velocities from 3 to 9 km/h. We demonstrate that using a set of simple features (variance, amplitude, RMS) a classification rate of more than 95% can be obtained. Misclassifications are mainly found at higher velocities (9 and 11 km/h) due to severe inter-subject differences in the acceleration signals. "


    In: Proc. of the 6th IASTED Int. Conf. on Biomechanics, ACTA Press, 2011.
  • Jungeblut, Thorsten; Ax, Johannes; Sievers, Gregor; Hübener, Boris; Porrmann, Mario; Rückert, Ulrich:
    Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited).
    In: Proc. of the Radar, Communication and Measurement Conference (RADCOM), 2011. »»
    Fulltext (PDF)

    conference paper / id: 2476993

  • Griessl, René; Herbrechtsmeier, Stefan; Porrmann, Mario; Rückert, Ulrich:
    A Low-Power Vision Processing Platform for Mobile Robots.
    In: Proceedings of the FPL2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures, 2011. »»
    Fulltext (external) Abstract

    conference paper / id: 2494510

    A Low-Power Vision Processing Platform for Mobile Robots

    Griessl, René; Herbrechtsmeier, Stefan; Porrmann, Mario; Rückert, Ulrich

    The paper proposes an implementation for a highly customizable FPGA-based vision processing module for mobile applications. The module can be ditrectly integrated into the AMiRo mini robot to anhance the robot’s vision processing capabilities while significantly reducing the CPU load. Dynamic reconfiguration can be utilized to further improve the resource utilization of the platform.


    In: Proceedings of the FPL2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures, 2011.
  • Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Puntsri, Kidsanapong; Rückert, Ulrich; Noé, Reinhold:
    Realtime Implementation of Square 16-QAM Transmission System.
    In: SPIE Eco-Photonics, Proc. SPIE 8065, 806519, 2011. »»
    Abstract

    conference paper / id: 2406730

    Realtime Implementation of Square 16-QAM Transmission System

    Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Puntsri, Kidsanapong; Rückert, Ulrich; Noé, Reinhold

    Combination of quadrature amplitude modulation with coherent detection is attractive for optical transmission systems, since it permits an increase of data rate without increasing the symbol rate or the required bandwidth. 16-point Quadrature Amplitude Modulation (16-QAM) is most interesting in this context. In-phase (I) and quadrature (Q) signals transmit 2 bit each. Together with polarization division multiplex this amounts to 8 bit/symbol. 2.5 Gbit/s synchronous coherent 16-QAM data is transmitted and received in a realtime intradyne setup with BER below FEC (7% overhead) threshold. A phase noise tolerant feedforward carrier recovery concept with hardware-efficient implementation was tested. Transmission was error-free in a back-to-back electrical test for various PRBS lengths. The carrier recovery does not contain any feedback loop and is therefore highly tolerant against laser phase noise.


    In: SPIE Eco-Photonics, Proc. SPIE 8065, 806519, 2011.
  • Sterpone, L.; Margaglia, F.; Köster, M.; Hagemeyer, Jens; Porrmann, Mario:
    Analysis of SEU Effects in Partially Reconfigurable SoPCs..
    In: Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011), 2011. »»
    Abstract

    conference paper / id: 2493819

    Analysis of SEU Effects in Partially Reconfigurable SoPCs.

    Sterpone, L.; Margaglia, F.; Köster, M.; Hagemeyer, Jens; Porrmann, Mario

    Systems on Programmable Chips (SoPCs) are receiving an increasing interest from various application domains. Safety critical missions, driven by space and avionics applications, are especially attracted in using SoPCs due to low non-recurring engineering costs, reconfigurability and the large number of logic resources they provide. The capability of partial reconfiguration has recently become a promising approach to enhance the flexibility of a given system and to adapt and customize to different requirements. However, Single Event Upsets (SEUs) induced by radiation environment where space and avionics system operate, have a critical and catastrophic effect in these devices. In this paper, we propose a novel algorithm, which is able to identify critical SEUs corrupting the functionality of a SoPC using dynamic and partial reconfiguration. The algorithm is based on an analyzer able to interact with the dynamic system components containing partial reconfiguration modules, the communication infrastructure and the static region. Efficient critical SEUs estimation depends not only on the independent component mapping but also on the routing interaction between reconfigurable modules placed in different feasible positions. The analysis algorithm has been proven on a partially reconfigurable platform using different applications, besides it has been validated by means of fault injection campaigns of SEUs into SoPC's configuration memory. The experimental results demonstrated the effectiveness of the developed algorithm. Fault injection results have been accurately investigated and commented.


    In: Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011), 2011.
  • Romoth, Johannes; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich:
    Fast Design-space Exploration with FPGA Cluster.
    In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011. »»
    Fulltext (external) Abstract

    conference paper / id: 2494507

    Fast Design-space Exploration with FPGA Cluster

    Romoth, Johannes; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich

    Clusters of FPGAs are a promising environment for prototyping and evaluation of new MPSoC architectures with a large number of parallel cores. The high complexity of both the MPSoC and the FPGA cluster pose many challenges for the designer [1]. Tools like Synopsys Certify can be used to automatically partition designs on systems with a fixed communication infrastructure, still they do not address the problem that minor changes in the design might require a whole rerun of the mapping procedure. For each FPGA the architecture mapping consists of synthesis, place & route, bitstream generation, and finally the FPGA configuration. While the configuration is done within milliseconds, synthesis, place & route, and bitstream generation easily take several hours to complete. Thus, the evaluation of different architectural variants becomes a very time-consuming task.


    In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.
  • Wilhelm, Per:
    IT-gestützte Leistungsmessung im Sport : System und Anwendung.
    In: Universität Bielefeld, 2011. »»
    Fulltext (PDF) Abstract

    thesis / id: 2507831

    IT-gestützte Leistungsmessung im Sport : System und Anwendung

    Wilhelm, Per

    Der Mensch stellt ein hochkomplexes System mit vielen sich beeinflussenden Teilsystemen dar. Um gezielt bestimmte Bereiche zu regeln sind Diagnosewerkzeuge erforderlich, die den aktuellen Zustand der Strecke Mensch erfassen. Diese Werkzeuge können z.B. zur präventiven Überwachung oder Optimierung der Leistung, etwa der Ausdauerleistungsfähigkeit im Sport, eingesetzt werden. Im Rahmen dieser Arbeit wird ein Konzept und dessen technische Umsetzung zur Erfassung und Analyse leistungsdiagnostischer Daten vorgestellt. Der Fokus liegt dabei im Speziellen auf Hallenmannschaftssportarten, bei denen vielfältige Bewegungsmuster auftreten können und es zu physischer Interaktion zwischen den Sportlern kommen kann. Ermittelt werden dabei Daten über die äußere Belastung (Parameter: Laufwege, Geschwindigkeit) mithilfe einer halb automatischen Videoanalyse sowie Werte über die innere Beanspruchung (Parameter: Herztätigkeit) durch den Einsatz von Sensorik in Sportkleidung. Aus technischer Sicht wurde ein System konzipiert, geplant, entwickelt, getestet und erfolgreich in Betrieb genommen, welches die oben aufgeführten Anforderungen erfüllt. Das videometrische System zur Messung der äußeren Belastung (kinematische Daten aus Spielerbewegungen) stellt ein passives Positionsbestimmungssystem dar, welches ohne Beeinträchtigung der Sportler eine genaue Geschwindigkeitsermittlung mit einer hohen zeitlichen und räumlichen Auflösung bereitstellt. Das drahtlose Sensornetzwerk ermöglicht die Aufnahme physiologischer Daten zur Abschätzung der inneren Beanspruchung. Das in der vorliegenden Arbeit hergeleitete Modell zur Messung leistungsdiagnostischer Daten im Sport wird in seiner Abstraktion von der Mehrheit der Sportwissenschaftler (Sportmediziner und Bewegungswissenschaftler) als korrekt angesehen und stellt mit dem Wirkungsgrad als Leistungsindex einen übergeordneten und neuartigen Parameter zur Verfügung. Das in dieser Arbeit entwickelte System zur Leistungserfassung richtet sich an Sportwissenschaftler, die Interesse an leistungsdiagnostischen Daten von Sportlern während eines Trainings oder Wettkampfes haben. Eine spätere kommerzielle Nutzung durch Trainer oder Medienanstalten ist vorgesehen und geplant. Aus sportwissenschaftlicher Sicht kann mit dem entwickelten System eine Bewertung der physiologischen und physikalischen Leistung für Sportler in ihrer gewohnten Umgebung im Training oder Wettkampf erstellt werden, was bisher nicht möglich war. Aktivitäten einzelner Spieler oder einer ganzen Mannschaft können nun erstmals abseits von Laboren im Feld(versuch) aufgezeichnet und analysiert werden. Trainer und Sportwissenschaftler haben damit Daten zur Verfügung, die den aktuellen und individuellen Beanspruchungsgrad dokumentieren. Damit ist es möglich, das tatsächliche Anforderungsprofil von Spiel- und Ballsportarten im Wettkampf darzustellen und die ermittelten Erkenntnisse in eine individuelle Trainings- sowie optimale Wettkampfgestaltung einfließen zu lassen. Die Kopplung physiologischer und kinematischer Daten stellt sowohl aus System- als auch aus Anwendersicht den innovativen Charakter dieser Arbeit dar.


    In: Universität Bielefeld, 2011.
  • Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Rückert, Ulrich; Noé, Reinhold:
    Synchronous 16-QAM Transmission in a FPGA-Based Coherent Receiver with Different Phase Estimation Filter Lengths.
    In: Volume: 228, ITG-Fachtagung vom 2.-3. Mai 2011, VDE-Verlag, 2011. »»
    Fulltext (external) Abstract

    conference paper / id: 2406708

    Synchronous 16-QAM Transmission in a FPGA-Based Coherent Receiver with Different Phase Estimation Filter Lengths

    Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Rückert, Ulrich; Noé, Reinhold

    In this article we present the implementation of a 16-QAM transmission system with feedforward realtime synchronous demodulation and data recovery. Different filter lengths (half-width N) were evaluated and a realtime data throughput of 2.5 Gbit/s was achieved. The 625 Mbaud (4x625 Mb/s) data is transmitted over one span of single-mode fiber, and is received in a realtime I&Q homodyne setup with standard external cavity laser. For powers larger than -30dBm, the average bit error rate (BER) is below forward-error correction (FEC) limit (7% overhead).


    In: Volume: 228, ITG-Fachtagung vom 2.-3. Mai 2011, VDE-Verlag, 2011.
  • Hoffmann, Sebastian; Al-Bermani, Ali; Wördehoff, Christian; Rückert, Ulrich; Noé, Reinhold:
    Kohärente optische 16-QAM-Übertragung mit ressourceneffizienter Vorwärts-Phasenschätzung.
    In: Workshop der ITG-Fachgruppe 5.3.1, 2011. »»
    Fulltext (PDF)

    conference paper / id: 2406796

  • Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Peau, Timo; Rückert, Ulrich; Noe, Reinhold:
    Synchronous Demodulation of Coherent 16-QAM with Feedforward Carrier Recovery.
    In: IEICE Transactions on Communications, Volume: E94-B, Institute of Electronics, Information and Communications Engineers (IEICE), 2011. »»
    Abstract

    article / id: 2307141

    Synchronous Demodulation of Coherent 16-QAM with Feedforward Carrier Recovery

    Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Peau, Timo; Rückert, Ulrich; Noe, Reinhold

    We present the recovery of 2.5 Gb/s synchronous 16-point quadrature amplitude modulation data in real-time for an linewidth-times-symbol-duration ratio of 0.00048 after transmission over 1.6 km standard single mode fiber.


    In: IEICE Transactions on Communications, Volume: E94-B, Institute of Electronics, Information and Communications Engineers (IEICE), 2011.
  • Jungeblut, Thorsten:
    Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren.
    In: 2011. »»

    thesis / id: 2687428

  • Blesken, Matthias W.; Chebil, Anouar; Rückert, Ulrich; Esquivel, Xavier; Schuetze, Oliver:
    Integrated circuit optimization by means of evolutionary multi-objective optimization.
    In: Proceedings of the 13th annual conference on Genetic and evolutionary computation, ACM, 2011. »»
    Fulltext (external) Abstract

    conference paper / id: 2551440

    Integrated circuit optimization by means of evolutionary multi-objective optimization

    Blesken, Matthias W.; Chebil, Anouar; Rückert, Ulrich; Esquivel, Xavier; Schuetze, Oliver

    The design of resource efficient integrated circuits (ICs) requires solving a minimization problem which consists of more than one objective given as measures of the available resources. This multi-objective optimization problem (MOP) can be solved on the smallest unit of the IC, the standard cells, to improve the performance of the entire circuit. In this work, transistor sizing of an IC is approached via a multi-objective approach which includes the use of multi-objective evolutionary algorithms (MOEAs). We compare the performance of two MOEAs on a four-dimensional MOP of a particular standard cell. The results indicate that evolutionary strategies are suitable for the treatment of such problems and advantageous against other rather classical methods.


    In: Proceedings of the 13th annual conference on Genetic and evolutionary computation, ACM, 2011.
  • Nava, F.; Sciuto, D.; Santambrogio, M. D.; Herbrechtsmeier, Stefan; Porrmann, Mario; Witkowski, U.; Rückert, Ulrich:
    Applying dynamic reconfiguration in the mobile robotics domain: a case study on computer vision algorithms..
    In: ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume: 4, Association for Computing Machinery (ACM), 2011. »»
    Abstract

    article / id: 2493623

    Applying dynamic reconfiguration in the mobile robotics domain: a case study on computer vision algorithms.

    Nava, F.; Sciuto, D.; Santambrogio, M. D.; Herbrechtsmeier, Stefan; Porrmann, Mario; Witkowski, U.; Rückert, Ulrich

    Mobile robots are widely used in industrial environments and are expected to be widely available in human environments in the near future, for example, in the area of care and service robots. This article proposes an implementation for a highly customizable color recognitionmodule based on Field Programmable Gate Array (FPGA) hardware to accomplish tasks like real-time frame processing for image streams. In comparison to a pure software solution on a CPU, an attached FPGA-based hardware accelerator enables real-time image processing and significantly reduces the required computing power of the CPU. Instead, the CPU can be used for tasks that cannot be efficiently implemented on FPGAs, for example, because of a large control overhead. We concentrate on a multirobot scenario where a group of robots follows a human team member by keeping a specific formation in order to support the human in exploration and object detection. Additionally, the robots provide a communication infrastructure to maintain a stable multihop communication network between the human and a base station recording all actions and evaluating the captured images and transmitted data. Depending on the current operating conditions, the robot system has to be able to execute a wide variety of different tasks. Since only a small number of tasks have to be executed concurrently, dynamic reconfiguration of the FPGA can be used to avoid the parallel implementation of all tasks on the FPGA. Within this context, this article discusses application fields where dynamic reconfiguration of FPGA-based coprocessors significantly reduces the CPU load and presents examples of how dynamic reconfiguration can be used in exploration


    In: ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume: 4, Association for Computing Machinery (ACM), 2011.
  • Noé, Reinhold; Hoffmann, Sebastian; Wördehoff, Christian; Al-Bermani, Ali; El-Darawy, Mohamed:
    Advances in Coherent Optical Modems and 16-QAM Transmission with Feedforward Carrier Recovery.
    In: Proc. SPIE 7960, 79600L, 2011. »»
    Abstract

    conference paper / id: 2406803

    Advances in Coherent Optical Modems and 16-QAM Transmission with Feedforward Carrier Recovery

    Noé, Reinhold; Hoffmann, Sebastian; Wördehoff, Christian; Al-Bermani, Ali; El-Darawy, Mohamed

    Polarization multiplexing and quadrature phase shift keying (QPSK) both double spectral efficiency. Combined with synchronous coherent polarization diverse intradyne receivers this modulation format is ultra-robust and cost-efficient. A feedforward carrier recovery is required in order to tolerate phase noise of normal DFB lasers. Signal processing in the digital domain permits compensation of at least chromatic and polarization mode dispersion. Some companies have products on the market, others are working on them. For 100 GbE transmission, 50 GHz channel spacing is sufficient. 16ary quadrature amplitude modulation (16-QAM) is attractive to double capacity once more, possibly in a modulation format flexible transponder which is switched down to QPSK only if system margin is too low. For 16-QAM the phase noise problem is sharply increased. However, also here a feedforward carrier recovery has been implemented. A number of carrier phase angles is tested in parallel, and the recovered data is selected for that phase angle where squared distance of recovered data to the nearest constellation point, averaged over a number of symbols, is minimum. An intradyne/selfhomodyne synchronous coherent 16-QAM experiment (2.5 Gb/s, 81 km) is presented.


    In: Proc. SPIE 7960, 79600L, 2011.
  • Korf, Sebastian; Cozzi, Dario; Koester, Markus; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich; Santambrogio, M.D.:
    Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs.
    In: Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on, 2011. »»
    Fulltext (external) Abstract

    conference paper / id: 2286173

    Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs

    Korf, Sebastian; Cozzi, Dario; Koester, Markus; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich; Santambrogio, M.D.

    The regularity of resources found in FPGAs is a unique feature, which can be utilized in a number of applications, e.g., in timing critical applications or applications with a demand for homogeneous routing. Current synthesis tools do not support an automatic generation of homogeneous FPGA designs, such that a time-consuming hand-crafted design is required. We present a tool flow, which automatically generates homogeneous hard macros for Xilinx FPGAs starting from a high-level description, such as VHDL. Key functionalities of the tool flow are a homogeneous placer and a suitable routing algorithm, which aim at maintaining the homogeneity of the resulting hard macro. The place and route tools use a resource library that is automatically generated for the target FPGA family by extracting relevant information from the vendor tools. The tool chain is demonstrated for the design of hard macros for a time-to-digital converter and a tiled partially reconfigurable region. The resulting designs are evaluated with respect to resource requirements and timing constraints.


    In: Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on, 2011.
  • Tanoto, Andry; Werner, Felix; Rückert, Ulrich; Li, Hanyi:
    Teleworkbench: Validating Robot Programs from Simulation to Prototyping with Minirobots (Demonstration).
    In: AAMAS 2011, 2011. »»

    Teleworkbench: Validating Robot Programs from Simulation to Prototyping with Minirobots (Demonstration)

    Tanoto, Andry; Werner, Felix; Rückert, Ulrich; Li, Hanyi

    This paper describes a Demo showing the role of the Teleworkbench in the validation process of a multi-agent system, e.g., a traffic management system. In the Demo, we show the capability of the Teleworkbench in seamlessly bridging the simulation and experimentation with real robots. During experiments, important information is logged for analysis purpose. Additionally, a graphical user interface enables geographically distributed users to perform some levels of interactivity, e.g., watch the video or command the robots.


    In: AAMAS 2011, 2011.
  • Köster, Markus; Hagemeyer, Jens; Margaglia, Fabio; Porrmann, Mario; Dittmann, Florian; Ditze, Michael; Sterpone, Luca; Harris, Julian; Ilstad, Jorgen:
    Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications.
    In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011. »»
    Fulltext (external) Abstract

    conference paper / id: 2494497

    Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications

    Köster, Markus; Hagemeyer, Jens; Margaglia, Fabio; Porrmann, Mario; Dittmann, Florian; Ditze, Michael; Sterpone, Luca; Harris, Julian; Ilstad, Jorgen

    Sensor technology continues to improve at the price of increased data rates, which require being processed. In the space domain, the available bandwidth for effectively transferring the data to the base station is limited, such that there is a need for a high-performance data processing unit on board of the spacecraft. This work targets the development of a scalable high-performance payload data processing system based on dynamically reconfigurable FPGAs. The system, which is called Dynamically Reconfigurable Processing Module (DRPM), enables a multitude of high performance data processing applications to be supported by the same hardware in space. While reconfigurable hardware offers higher performances than traditional DSP-based solutions, it also supports the same flexibility to modify the functionality at run-time.


    In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.
  • El-Darawy, M.; Pfau, T.; Wördehoff, Christian; Hoffmann, S.; Noe, R.:
    Realtime QPSK transmission with an integrated coherent optical receiver frontend.
    In: Photonics Society Summer Topical Meeting Series, 2011 IEEE, 2011. »»
    Abstract

    conference paper / id: 2406701

    Realtime QPSK transmission with an integrated coherent optical receiver frontend

    El-Darawy, M.; Pfau, T.; Wördehoff, Christian; Hoffmann, S.; Noe, R.

    An integrated coherent receiver frontend is compared to a fiber-pigtailed 90° hybrid in a realtime QPSK transmission experiment. Additionally the impact of carrier recovery filter width and phase deviations in the 90° hybrid is analyzed.


    In: Photonics Society Summer Topical Meeting Series, 2011 IEEE, 2011.
  • Grawinkel, M.; Schäfers, Thorsten; Brinkmann, A.; Hagemeyer, Jens; Porrmann, Mario:
    Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability..
    In: MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems., 2011. »»
    Fulltext (external) Abstract

    conference paper / id: 2493823

    Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.

    Grawinkel, M.; Schäfers, Thorsten; Brinkmann, A.; Hagemeyer, Jens; Porrmann, Mario

    Exponentially growing capacities of disk drives have increased the problem that not only a complete disk can fail, but also individual, small groups of sectors can be erroneous. These sector errors are especially critical during RAID rebuilds because they can only be detected when the corresponding sectors are read. Mechanisms to cope with sector errors, therefore, have become an important way to improve disk reliability. One approach to deal with sector errors is the introduction of intra-disk redundancy, where additional redundancy blocks are calculated and stored for each set of disk sectors. Previous studies have introduced intra-disk redundancy schemes and have evaluated their impact on disk reliability. None of these studies has evaluated the influence on disk drive performance or the underlying energy consumption. The study presented in this paper benchmarks existing schemes concerning these metrics. It shows the surprising result that weaker codes combined with newly introduced scrambling techniques can produce faster layouts with similar reliability properties than previously proposed strong codes.


    In: MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems., 2011.
  • Gausemeier, Jürgen; Schierbaum, Thomas; Dumitrescu, Roman; Herbrechtsmeier, Stefan; Jungmann, Alexander:
    Miniature Robot BeBot: Mechatronic Test Platform for Self-X Properties.
    In: Proceedings of the 9th IEEE International Conference on Industrial Informatics (INDIN), IEEE, 2011. »»

    conference paper / id: 2500887

2010
  • Adelt, Philipp; Kleinjohann, Bernd; Herbrechtsmeier, Stefan; Rückert, Ulrich:
    Demonstrating self-optimization using a heterogeneous robot group.
    In: Proceedings of the 8th IEEE International Conference on Industrial Informatics, International Conference on Industrial Informatics (INDIN) ; 8, IEEE, 2010. »»
    Abstract

    conference paper / id: 2018485

    Demonstrating self-optimization using a heterogeneous robot group

    Adelt, Philipp; Kleinjohann, Bernd; Herbrechtsmeier, Stefan; Rückert, Ulrich

    Self-optimization is a concept for mechatronic systems to leave open the choice among system objectives as a degree of freedom until runtime to allow better adaptation to changing system and environment conditions. Demonstration and knowledge transfer of the concept is not easy as the effects of it in mechatronic systems are hard to see in a complex system. To further spread the idea of self-optimization, an intuitive anchor is needed to make it easier to talk about the concept. Also the abstraction from technical details facilitates focusing on the concept. We have developed a multi-agent heterogeneous robotic demonstrator that allows showing the process of self-optimization on a timescale of minutes. The demonstrator decomposes the roles in a mechatronic system to robotic agents. An association between a function and the behavior of the robot is achieved. After having demonstrated the setup for expert and non-expert audiences we have seen the encouraging effect that discussions spin off easily and allow to spread the idea effectively. We present the concept of self-optimization, the behavior-based demonstrator scenario implemented using BeBot miniature and Paderkicker robots in an office environment.


    In: Proceedings of the 8th IEEE International Conference on Industrial Informatics, International Conference on Industrial Informatics (INDIN) ; 8, IEEE, 2010.
  • Al Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Puntsri, K.; Pfau, Timo; Rückert, Ulrich; Noe, Reinhold:
    Realtime 16-QAM Transmission with Coherent Digital Receiver.
    In: OECC 2010, IEEE Xplore, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2018497

    Realtime 16-QAM Transmission with Coherent Digital Receiver

    Al Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Puntsri, K.; Pfau, Timo; Rückert, Ulrich; Noe, Reinhold

    We present the recovery of 2.5 Gb/s synchronous 16-point quadrature amplitude modulation data in real-time for an linewidth-times-symbol-duration ratio of 0.00048 after transmission over 1.6 km standard single mode fiber.


    In: OECC 2010, IEEE Xplore, 2010.
  • al Bermani, Ali; Wördehoff, Christian; Pfau, Timo; Hoffmann, Sebastian; Rückert, Ulrich; Noe, Reinhold:
    First Realtime Synchronous 16-QAM Transmission with Coherent Digital Receiver.
    In: 11. ITG-Fachtagung "Photonische Netze", Volume: 222, ITG/VDE, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2018505

    First Realtime Synchronous 16-QAM Transmission with Coherent Digital Receiver

    al Bermani, Ali; Wördehoff, Christian; Pfau, Timo; Hoffmann, Sebastian; Rückert, Ulrich; Noe, Reinhold

    This letter presents for the first time 1.25 Gb/s synchronous coherent 16-point Quadrature Amplitude Modulation (16-QAM) transmitted and received data in a real-time homodyne setup with external cavity laser (ECL). For powers larger than ?20dBm, the average bit error rate (BER) is below forward-error correction (FEC) limit.


    In: 11. ITG-Fachtagung "Photonische Netze", Volume: 222, ITG/VDE, 2010.
  • Herbrechtsmeier, Stefan; El Habbal, Mohamed Ahmed Mostafa; Rückert, Ulrich; Witkowski, Ulf:
    Robust Multihop Communication for Mobile Applications.
    In: Proceedings of IARP Workshop on Robotics for Risky Interventions and Environmental Surveillance (RISE) 2010, RISE 2010, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2018517

    Robust Multihop Communication for Mobile Applications

    Herbrechtsmeier, Stefan; El Habbal, Mohamed Ahmed Mostafa; Rückert, Ulrich; Witkowski, Ulf

    This paper focuses on node placement strategy, communication protocols and hardware implementation of a robust mobile multi-hop network. As part of the GUARDIANS project a main disaster scenario of a large industrial warehouse on fire is assumed. In this scenario, black smoke may fill large space of the warehouse which makes it very difficult for the firefighters to locate themselves and orientate in the building. In our approach a multi-hop ad-hoc network communication system is able to provide a robust communication system. Focus of this paper is the distribution of robots to guaranteeing robust communication between the base station outside the scenario area and the fire fighter inside the building. Concerning the first point, the presence of smoke and the indoor nature of our scenario prevent localization using camera and GPS respectively. Therefore the performance and accuracy of other sensors were tested in order to examine their usability and reliability in such a scenario, like ultra-sound, laser and radio signaling. The second point is the evaluation of routing protocols and the development of a mobile communication gateway which is optimized for the mobile usage and therefore supports different techniques for energy saving. Its characteristic was tested in different scenarios like a complex building and a parking garage.


    In: Proceedings of IARP Workshop on Robotics for Risky Interventions and Environmental Surveillance (RISE) 2010, RISE 2010, 2010.
  • Dreesen, Ralf; Jungeblut, Thorsten; Thies, Michael; Kastens, Uwe:
    Dependence Analysis of VLIW Code for Non-Interlocked Pipelines.
    In: Proceedings of the 8th Workshop on Optimizations for DSP and Embedded Systems, ODES-8, 2010. »»

    Dependence Analysis of VLIW Code for Non-Interlocked Pipelines

    Dreesen, Ralf; Jungeblut, Thorsten; Thies, Michael; Kastens, Uwe

    Data dependence analysis (DDA) on assembly code is a frequent problem in compilers and program analysis tools. The fundamentals of a DDA on code for simple processors are well understood. We propose a DDA method, that is applicable for a wider range of processors. This includes VLIW processors and processors with delayed branches and delayed register accesses. For these architectures, the instruction order may no longer match the order of register accesses, which necessitates a new analysis technique. The result of our analysis method is an instruction dependence graph (IDG), which also contains information on minimal instruction distances. For the mentioned architectures and allocated registers, the IDG may be cyclic. We discuss this phenomenon and outline analgorithm to reschedule such IDGs. We successfully implemented the DDA method and a respective scheduler in our compiler for the CoreVA VLIW architecture.


    In: Proceedings of the 8th Workshop on Optimizations for DSP and Embedded Systems, ODES-8, 2010.
  • Noe, Reinhold; Hoffmann, Sebastian; Wördehoff, Christian; El-Darawy, Mohamed:
    Digital Coherent Transmission Systems.
    In: Signal Processing in Photonic Communications, SPPCom, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2019072

    Digital Coherent Transmission Systems

    Noe, Reinhold; Hoffmann, Sebastian; Wördehoff, Christian; El-Darawy, Mohamed

    Polarization-multiplexed QPSK transmission with synchronous coherent digital intradyne receivers has become a megatrend and is expected to provide cost- and spectrally efficient 100 GbE transmission with 50 GHz optical channel spacing.


    In: Signal Processing in Photonic Communications, SPPCom, 2010.
  • Koester, M.; Luk, W.; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich:
    Design Optimizations for Tiled Partially Reconfigurable Systems.
    In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 19, Institute of Electrical & Electronics Engineers (IEEE), 2010. »»
    Abstract

    article / id: 2145423

    Design Optimizations for Tiled Partially Reconfigurable Systems

    Koester, M.; Luk, W.; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich

    In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. Dynamic system components are represented by partial reconfiguration (PR) modules. In comparison to a static system, the design of a partially reconfigurable system requires additional design steps, such as partitioning the device resources into static and dynamic regions. We present the concept of tiled PR regions, which enables a flexible online-placement of PR modules. Dynamic reconfiguration requires a suitable communication infrastructure to interconnect the static and dynamic system components. We present an embedded communication macro, a communication infrastructure that interconnects PR modules in a tiled PR region. Efficient online-placement of PR modules depends not only on the placement algorithm, but also on design-time aspects such as the chosen synthesis regions of the PR modules. We propose a design method for selecting suitable synthesis regions for the PR modules aiming to optimize their placement at run-time.


    In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 19, Institute of Electrical & Electronics Engineers (IEEE), 2010.
  • Porrmann, Mario; Hagemeyer, Jens; Pohl, Christopher; Romoth, Johannes; Strugholtz, Manuel:
    RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing.
    In: Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing, Volume: 19, IOS press, 2010. »»

    conference paper / id: 2472693

  • Christ, Peter; Mielebacher, Jörg; Haag, Martin; Rückert, Ulrich; Bredford, Anthony; Owens, Matthew:
    Detection of Body Movement and Measurement of Physiological Stress with a Mobile Chest Module in Obesity Prevention.
    In: Australasian Conference on Mathematics and Computers in Sport, 2010. »»

    conference paper / id: 1940858

  • Hoffmann, Sebastian; Wördehoff, Christian; al Bermani, Ali; Rückert, Ulrich; Noe, Reinhold:
    Hardware-effiziente Phasenschätzung für kohärenten QAM-Empfang mit regulären Stern-Konstellationen.
    In: 11. ITG-Fachtagung "Photonische Netze", Volume: 222, ITG/VDE, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2018530

    Hardware-effiziente Phasenschätzung für kohärenten QAM-Empfang mit regulären Stern-Konstellationen

    Hoffmann, Sebastian; Wördehoff, Christian; al Bermani, Ali; Rückert, Ulrich; Noe, Reinhold

    Wir stellen eine Phasenschätzmethode vor, die für alle QAM-Übertragungssysteme geeignet ist, bei denen die Symbole auf Ursprungsgeraden (Strahlen) mit einheitlichem Winkelabstand angeordnet sind (reguläre Stern-Konstellationen). Für diese QAM-Schemata bietet sich eine Datenrückgewinnung in Polarkoordinaten an. Dabei wird nur die Phase des empfangenen Signals benötigt, nicht jedoch dessen Amplitude. Diese Eigenschaft erlaubt es ohne weitere Koordinatenumwandlungen und komplexe Berechnungen direkt winkelbasiert zu einer geschätzten Phase zu gelangen. Unsere Methode eignet sich insbesondere für kohärente Übertragungssysteme mit DFB-Lasern, bei denen ein hohes Phasenrauschen auftritt.


    In: 11. ITG-Fachtagung "Photonische Netze", Volume: 222, ITG/VDE, 2010.
  • Hoffmann, Sebastian; Wördehoff, Christian; Al-Bermani, Ali; El-Darawy, Mohamed; Puntsri, Kidsanapong; Rückert, Ulrich; Noe, Reinhold:
    Hardware-Efficient Phase Estimation for Digital Coherent Transmission With Star Constellation QAM.
    In: IEEE Photonics Journal, Volume: 2, Institute of Electrical & Electronics Engineers (IEEE), 2010. »»
    Abstract

    article / id: 1968122

    Hardware-Efficient Phase Estimation for Digital Coherent Transmission With Star Constellation QAM

    Hoffmann, Sebastian; Wördehoff, Christian; Al-Bermani, Ali; El-Darawy, Mohamed; Puntsri, Kidsanapong; Rückert, Ulrich; Noe, Reinhold

    In order to build optical transmission systems for 100 Gb/s and above on a single wavelength division multiplexing channel, transition from quadrature phase-shift keying (QPSK) to higher quadrature amplitude modulation (QAM) formats seems to be inevitable. Instead of the usual square constellation QAM, we focus on regular star constellation QAM formats and present a hardware-efficient phase-estimation algorithm that is suitable for all regular star constellations, together with preliminary simulation results.


    In: IEEE Photonics Journal, Volume: 2, Institute of Electrical & Electronics Engineers (IEEE), 2010.
  • Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Sandel, David; Rückert, Ulrich; Noe, Reinhold:
    Real-Time Phase-Noise-Tolerant 2.5-Gb/s Synchronous 16-QAM Transmission.
    In: IEEE Photonics Technology Letters, Volume: 22, Institute of Electrical & Electronics Engineers (IEEE), 2010. »»
    Abstract

    article / id: 1968280

    Real-Time Phase-Noise-Tolerant 2.5-Gb/s Synchronous 16-QAM Transmission

    Al-Bermani, Ali; Wördehoff, Christian; Hoffmann, Sebastian; Sandel, David; Rückert, Ulrich; Noe, Reinhold

    The 2.5-Gb/s coherent 16-quadrature amplitude modulation data is optically transmitted over 75 km and synchronously received by self-homodyning in a real-time in-phase and quadrature receiver, with bit-error ratio below forward-error correction threshold. To this purpose, a phase-noise-tolerant hardware-efficient feedforward carrier recovery was implemented.


    In: IEEE Photonics Technology Letters, Volume: 22, Institute of Electrical & Electronics Engineers (IEEE), 2010.
  • Dittmann, Florian; Linke, M.; Hagemeyer, Jens; Köster, Markus; Lallet, Julien; Pohl, Christopher; Porrmann, Mario; Harris, Julian; Ilstad, Jorgen:
    Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks..
    In: Proceedings of the International SpaceWire Conference 2010, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2493826

    Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks.

    Dittmann, Florian; Linke, M.; Hagemeyer, Jens; Köster, Markus; Lallet, Julien; Pohl, Christopher; Porrmann, Mario; Harris, Julian; Ilstad, Jorgen

    The ESA-project "FPGA based generic module and dynamic reconfigurator" targets the development of a hardware architecture, called DRPM (for Dynamically Reconfigurable Processing Module). The goal of the DRPM is to develop a system that allows for the adaptation of hardware components in flight at run-time. This is enabled by the implementation of an SRAM-FPGA-based partially reconfigurable core, which is embedded into a system hosting a reconfiguration controller and a system controller providing suitable interfaces for space applications. Maximum flexibility is realized by implementing SpaceWire interfaces that enable the DRPM integration into a SpaceWire network. Moreover, the SpaceWire RMAP protocol is used for remote access to registers and memory banks of the DRPM.


    In: Proceedings of the International SpaceWire Conference 2010, 2010.
  • Blesken, M.; Lütkemeier, Sven; Rückert, Ulrich:
    Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells.
    In: Proc. IEEE Int Circuits and Systems (ISCAS) Symp, 2010. »»
    Abstract

    conference paper / id: 2475069

    Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells

    Blesken, M.; Lütkemeier, Sven; Rückert, Ulrich

    Transistor sizing of sub-threshold standard cells for digital ultra-low power systems is a very challenging task because robustness has to be considered as an important design objective in addition to the competing resources power consumption and propagation delay. In this paper we regard this task as a multiobjective optimization problem (MOP) and show that the support of MOP algorithms is necessary and beneficial in the design process of sub-threshold CMOS logic standard cells. Optimization results are presented for an inverter, NAND gate, and NOR gate in a 65 nm process technology.


    In: Proc. IEEE Int Circuits and Systems (ISCAS) Symp, 2010.
  • Lütkemeier, Sven; Rückert, Ulrich:
    A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror.
    In: IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 57, Institute of Electrical & Electronics Engineers (IEEE), 2010. »»
    Abstract

    article / id: 1929613

    A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror

    Lütkemeier, Sven; Rückert, Ulrich

    In this brief, we propose a novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels. In contrast to other existing implementations, it does not require a static current flow and can therefore offer considerable static power savings. The circuit has been optimized and simulated in a 90-nm process technology. It operates correctly across process corners for supply voltages from 100 mV to 1 V on the low-voltage side. At the target design voltage of 200 mV, the level shifter has a propagation delay of 18.4 ns and a static power dissipation of 6.6 nW. For a 1-MHz input signal, the total energy per transition is 93.9 fJ. Simulation results are compared to an existing subthreshold to above-threshold level shifter implementation from the paper of Chen et al.


    In: IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 57, Institute of Electrical & Electronics Engineers (IEEE), 2010.
  • al Bermani, Ali; Noe, Reinhold; Hoffmann, Sebastian; Wördehoff, Christian; Rückert, Ulrich; Pfau, Timo:
    Implementation of Coherent 16-QAM Digital Receiver with Feedforward Carrier Recovery.
    In: Signal Processing in Photonic Communications, SPPCom, IEEE Xplore, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2018490

    Implementation of Coherent 16-QAM Digital Receiver with Feedforward Carrier Recovery

    al Bermani, Ali; Noe, Reinhold; Hoffmann, Sebastian; Wördehoff, Christian; Rückert, Ulrich; Pfau, Timo

    1.25 Gbit/s synchronous coherent 16-QAM data is transmitted and received in a real-time intradyne setup with BER below FEC threshold. A phase noise tolerant feedforward carrier recovery concept with hardware-efficient implementation was tested.


    In: Signal Processing in Photonic Communications, SPPCom, IEEE Xplore, 2010.
  • Jungeblut, Thorsten; Puttmann, Christoph; Dreesen, Ralf; Porrmann, Mario; Thies, Michael; Rückert, Ulrich; Kastens, Uwe:
    Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography.
    In: Advances in Radio Science, Volume: 8, Copernicus GmbH, 2010. »»

    Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography

    Jungeblut, Thorsten; Puttmann, Christoph; Dreesen, Ralf; Porrmann, Mario; Thies, Michael; Rückert, Ulrich; Kastens, Uwe

    The secure transmission of data plays a significant role in todays information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the designspace exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.


    In: Advances in Radio Science, Volume: 8, Copernicus GmbH, 2010.
  • Christmann, W.; Strugholtz, M.; Hagemeyer, Jens; Porrmann, Mario:
    Mehrprozessor-Computersystem.
    In: 2010. »»

    patent / id: 2494087

  • Pohl, Christopher; Fuest, Ralf; Porrmann, Mario:
    vMAGIC – Automatic Code Generation for VHDL.
    In: newsletter edacentrum, Volume: 2009, Hindawi Publishing Corporation, 2010. »»
    Abstract

    article / id: 2494479

    vMAGIC – Automatic Code Generation for VHDL

    Pohl, Christopher; Fuest, Ralf; Porrmann, Mario

    Automatic code generation is a standard method in software engineering, improving the code reliability as well as reducing the overall development time. In hardware engineering, automatic code generation is utilized within a number of development tools, the integrated code generation functionality, however, is not exposed to developers wishing to implement their own generators. In this paper, VHDL Manipulation and Generation Interface (vMAGIC), a Java library to read, manipulate, and write VHDL code is presented. The basic functionality as well as the designflow is described, stressing the advantages when designing with vMAGIC. Two real-world examples demonstrate the power of code generation in hardware engineering.


    In: newsletter edacentrum, Volume: 2009, Hindawi Publishing Corporation, 2010.
  • Purnaprajna, Madhura; Porrmann, Mario; Rückert, Ulrich; Hussmann, Michael; Thies, Michael; Kastens, Uwe:
    Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis.
    In: ACM Transactions on Reconfigurable Technology, Volume: 3, Association for Computing Machinery (ACM), 2010. »»
    Abstract

    article / id: 2018557

    Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis

    Purnaprajna, Madhura; Porrmann, Mario; Rückert, Ulrich; Hussmann, Michael; Thies, Michael; Kastens, Uwe

    In multiprocessors, performance improvement is typically achieved by exploring parallelism with fixed granularities, such as instruction-level, task-level, or data-level parallelism. We introduce a new reconfiguration mechanism that facilitates variations in these granularities in order to optimize resource utilization in addition to performance improvements. Our reconfigurable multiprocessor QuadroCore combines the advantages of reconfigurability and parallel processing. In this article, a unified hardware-software approach for the design of our QuadroCore is presented. This design flow is enabled via compiler-driven reconfiguration which matches application-specific characteristics to a fixed set of architectural variations. A special reconfiguration mechanism has been developed that alters the architecture within a single clock cycle. The QuadroCore has been implemented on Xilinx XC2V6000 for functional validation and on UMC’s 90nm standard cell technology for performance estimation. A diverse set of applications have been mapped onto the reconfigurable multiprocessor to meet orthogonal performance characteristics in terms of time and power. Speedup measurements show a 2-11 times performance increase in comparison to a single processor. Additionally, the reconfiguration scheme has been applied to save power in data-parallel applications. Gate-level simulations have been performed to measure the power-performance trade-offs for two computationally complex applications. The power reports confirm that introducing this scheme of reconfiguration results in power savings in the range of 15-24%.


    In: ACM Transactions on Reconfigurable Technology, Volume: 3, Association for Computing Machinery (ACM), 2010.
  • Puttmann, Christoph; Porrmann, Mario; Grassi, Paolo Roberto; Santambrogio, Marco D.; Rückert, Ulrich:
    High Level Specification of Embedded Listeners for Monitoring of Network-on-Chips.
    In: Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS, 2010. »»
    Abstract

    conference paper / id: 2018564

    High Level Specification of Embedded Listeners for Monitoring of Network-on-Chips

    Puttmann, Christoph; Porrmann, Mario; Grassi, Paolo Roberto; Santambrogio, Marco D.; Rückert, Ulrich

    Nowadays, the Network-on-Chip (NoC) paradigm has become more and more popular for building an on-chip communication infrastructure. Like in every traditional network, debugging and performance monitoring are also very important issues in NoC-based systems. Unfortunately, the design process of monitoring hardware is a time consuming activity. The work presented in this paper is based on a high level specification language, called SiLLis (Simplified Language for Listeners), for the convenient development of generic monitoring hardware. SiLLis allows the designer to define complex filter rules on a high abstraction level. In this way, the design time as well as the bandwidth requirements for monitoring data can be drastically reduced. To present the benefits of SiLLis, we define a performance monitor that is integrated into a NoC-based multiprocessor System-on-Chip and can be used both to analyze the performance of the system and to optimize the routing strategy at run-time. By using SiLLis, the performance monitor can be realized with a area overhead of only 0.58 % per NoC node.


    In: Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS, 2010.
  • Jungeblut, Thorsten; Dreesen, R.; Porrmann, Mario; Thies, M.; Rückert, Ulrich; Kastens, U.:
    A Framework for the Design Space Exploration of Software-Defined Radio Applications.
    In: 2nd International ICST Conference on Mobile Lightweight Wireless Systems, 2010. »»

    A Framework for the Design Space Exploration of Software-Defined Radio Applications

    Jungeblut, Thorsten; Dreesen, R.; Porrmann, Mario; Thies, M.; Rückert, Ulrich; Kastens, U.

    This paper describes a framework for the design space exploration of resource-effcient software-defined radio architectures. This design space exploration is based on a dual design ow, using a central processor specification as reference for the hardware development and the automatic generation of a C-compiler based tool chain. Using our modular rapid prototyping environment RAPTOR and the RF-frontend DB-SDR1, functional verification of SDR applications can be performed. An 802.11b transmitter SDR implementation is mapped on our CoreVA VLIW architecture and evaluated in terms of execution time and energy consumption. By introducing application specific instruction set extensions and a dedicated hardware accelerator, execution time and energy consumption could be reduced by about 90 %.


    In: 2nd International ICST Conference on Mobile Lightweight Wireless Systems, 2010.
  • Jungeblut, Thorsten; Lütkemeier, Sven; Sievers, Gregor; Porrmann, Mario; Rückert, Ulrich:
    A modular design flow for very large design space explorations.
    In: CDNLive! EMEA 2010, 2010. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2286628

    A modular design flow for very large design space explorations

    Jungeblut, Thorsten; Lütkemeier, Sven; Sievers, Gregor; Porrmann, Mario; Rückert, Ulrich

    The design of application specific and resource efficient digital circuits, like complex multiprocessor system on chips, often requires to choose among multiple possible configurations affecting both performance and resource consumption. A design space exploration (DSE) of the different architecture configurations and multiple target libraries usually implies hundreds of syntheses. In sub-90nm-technologies place and route (P&R) has to be performed to derive realistic results. This complexity makes the design space exploration interminable. To compare different implementations within a company sets of generally accepted constraints are required. The product family of Cadence® Design Systems Inc. offers a large variety of tools for the design of microelectronic circuits to perform, for example, RTL synthesis, power estimation, place and route or verification. To speed up the iteration steps of the DSE, we have developed a semi-automatic tool flow, using the EDA environment of Cadence. This tool flow is used to perform the exploration of very large design spaces with, for example hundreds of RTL synthesis, only limited by the computational power available at our group. To minimize the iteration time and to maximize the efficiency of our EDA hardware, we developed a load balancing system to distribute jobs to different computers.


    In: CDNLive! EMEA 2010, 2010.
  • Hein, Sebastian; Mielebacher, Jörg; Christ, Peter; Haag, Martin:
    Preventing Physical Inactivity using a Mobile Chest Module.
    In: NCT-Congress Heidelberg on Exercise, Energy Balance and Cancer, 2010. »»

    conference paper / id: 1940945

  • Jungeblut, Thorsten; Sievers, Gregor; Porrmann, Mario; Rückert, Ulrich:
    Design Space Exploration for Memory Subsystems of VLIW Architectures.
    In: 5th IEEE International Conference on Networking, Architecture, and Storage, NAS 2010, 2010. »»
    Abstract

    conference paper / id: 2018549

    Design Space Exploration for Memory Subsystems of VLIW Architectures

    Jungeblut, Thorsten; Sievers, Gregor; Porrmann, Mario; Rückert, Ulrich

    In this work we present a design space exploration of the memory subsystem of our configurable CoreVA VLIW architecture. The development of resource efficient processor architectures is based on a two-stage tool flow using a high-level processor specification as a reference. We evaluate several memory configurations like one memory port or two memory ports, as well as different write-miss-allocation modes. Applications ranging from LTE protocol stack over baseband processing up to cryptography and multimedia are evaluated in terms of execution time and energy efficiency. Analyses have shown that the application specific configuration of the memory subsystem can improve energy by up to 25%. Our environment allows the rapid profiling and evaluation of algorithms to choose the most efficient configuration.


    In: 5th IEEE International Conference on Networking, Architecture, and Storage, NAS 2010, 2010.
  • Werner, Felix; Rückert, Ulrich; Tanoto, Andry; Welzel, Jaan:
    The Teleworkbench: A Platform for Performing and Comparing Experiments in Robot Navigation.
    In: Proceedings of the Workshop on The Role of Experiments in Robotics Research, ICRA 2010, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2018570

    The Teleworkbench: A Platform for Performing and Comparing Experiments in Robot Navigation

    Werner, Felix; Rückert, Ulrich; Tanoto, Andry; Welzel, Jaan

    Experiments are essential ingredients of science to compare, validate or refute theories, methodologies, hypotheses and approaches. However, in robotics, the comparison of methods using experiments is difficult because of the variety of robotic platforms and experiment environments. In this paper we describe the Teleworkbench and discuss the role it can take on the quest of creating repeatable and reproducible experiments in robot navigation, obtaining com- parable results as well as evaluating and analysing results. The Teleworkbench can control up to 64 mini-robots simultaneously, log user defined quantities for post-experiment analysis and monitor the experiments via cameras mounted in the ceiling. A web interface makes the Teleworkbench accessible for remotely located users. Thus, the Teleworkbench is a platform that robotic scientists can use in order to evaluate the developed approaches quantitatively and qualitatively as well as to com- pare their methods amongst each other.


    In: Proceedings of the Workshop on The Role of Experiments in Robotics Research, ICRA 2010, 2010.
  • Wilhelm, Per; Thomas, Patrick; Monier, Emad; Timmermann, Robert; Dellnitz, Michael; Werner, Felix; Rückert, Ulrich:
    An Integrated Monitoring and Analysis System for Performance Data of Indoor Sport Activities.
    In: The 10th Australasian Conference on Mathematics and Computers in Sport, 2010. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2018575

    An Integrated Monitoring and Analysis System for Performance Data of Indoor Sport Activities

    Wilhelm, Per; Thomas, Patrick; Monier, Emad; Timmermann, Robert; Dellnitz, Michael; Werner, Felix; Rückert, Ulrich

    The wish of many sports scientists and trainers is accessing performance diagnoses data of athletes during training or competition. This data concerns the external conditions (e.g. speed and distance) as well as the internal (physical) strain of the players. For collecting this performance data, we have developed an analysis system, consisting of a high resolution video-system together with a wireless sensor network. In order to record the physiological data (heart rate) of the athlete, a custom-built sensor module has been developed and integrated into a sports shirt. The integrated sensors collect the physiological data. Following the data collection some signal processing is optionally performed and the data is transmitted via a wireless communication technology to a central computer. We use an adopted Suunto Oy Foot Pod to measure online the current speed of an athlete and compute its overall distance through integration. In physical and tactical analysis of indoor sport games path information of the players is of great importance. In order to acquire players’ path information, a training session or game is captured by a video-system consisting of two cameras which are mounted in the ceiling of a sports hall. The video data is post-processed in order to identify positions of the players and to track all players on the field. The recorded data of the mobile devices can be processed and visualised online. For example during the sports event, the heart rate can be monitored and the trainer can decide on substituting a player based on his heart rate profile. Another application of our system is the substantial evaluation of the covered distance of basketball players per quarter. The results of this study will be presented in this paper.


    In: The 10th Australasian Conference on Mathematics and Computers in Sport, 2010.
  • El-Darawy, Mohamed; Pfau, Timo; Wördehoff, Christian; Noe, Reinhold:
    Performance of Modified Decision-Directed Polarization Control/Demultiplex Algorithm in Coherent QAM Receiver.
    In: Proc. OFC/NFOEC 2010, IEEE Xplore, 2010. »»
    Fulltext (external) Abstract

    conference paper / id: 2019035

    Performance of Modified Decision-Directed Polarization Control/Demultiplex Algorithm in Coherent QAM Receiver

    El-Darawy, Mohamed; Pfau, Timo; Wördehoff, Christian; Noe, Reinhold

    A modified decision-directed polarization control and demultiplex algorithm for coherent receivers is evaluated for QAM schemes up to order 256, and compared against the constant-modulus algorithm adapted for QAM and differential phase compensation.


    In: Proc. OFC/NFOEC 2010, IEEE Xplore, 2010.
  • Berge, A.H.K.O.; Blesken, B.M.; Aunet, C.S.; Rückert, Ulrich:
    Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach.
    In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, 2010. »»
    Abstract

    conference paper / id: 2286608

    Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach

    Berge, A.H.K.O.; Blesken, B.M.; Aunet, C.S.; Rückert, Ulrich

    In this paper we present design and optimization results of a 9T SRAM cell in a 65 nm low power technology, which previously has not been investigated for subthreshold operation. The cell is capable of both read and write operations on a supply voltage from 300mV to 1.2V. In our implementation the SRAM cell employs both high and low Vt devices for lower leakage and faster read operation. The current work focuses on operation of the cell as a single port SRAM, although extension to dual port is possible. To optimize and find trade-offs for SRAM performance in both voltage domains we use a multiobjective optimization method, where our design goals were robustness, leakage, operating speed and area. The optimization method provides an approximation of the set of all Pareto optimal designs. Based on this we may quickly select criteria for the objectives and easily optimize the rest of the parameters. Compared to recent publications the 9T cell of this paper shows promise of greatly reducing standby leakage power and good robustness while retaining a similar speed.


    In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, 2010.
  • Puttmann, Christoph; Porrmann, Mario; Rückert, Ulrich:
    Extending GigaNoC towards a Dependable Network-on-Chip.
    In: Digest of the DAC Workshop on Diagnostic Services in Network-on-Chips (DSNOC), 2010. »»
    Abstract

    conference paper / id: 2286622

    Extending GigaNoC towards a Dependable Network-on-Chip

    Puttmann, Christoph; Porrmann, Mario; Rückert, Ulrich

    With the continuing shrinking of CMOS technologies the susceptibility to operational faults increases and the design of reliable on-chip communication becomes crucially important. This paper focuses on the design of a faulttolerant and dependable Network-on-Chip (NoC) communication infrastructure. By adding error detecting codes to the communication channels, transient as well as permanent faults can be detected. All transmission faults are recognized by an integrated error counter and upon reaching a certain threshold, the on-chip communication infrastructure is reconfigured by an adaptive routing scheme.


    In: Digest of the DAC Workshop on Diagnostic Services in Network-on-Chips (DSNOC), 2010.
2009
  • Paier, Daniel; Schnittker, Reinhard; Reinecke, Kirsten; Wilhelm, Per; Preis, Robert; Weiß, Michael; Baumeister, Jochen:
    Physiologische Spielbeobachtung – Testgüte des Videotrackings im Sports Performance Analyzer (SPA).
    In: Deutsche Zeitschrift für Sportmedizin, Volume: 60, 2009. »»
    Abstract

    article / id: 2295204

    Physiologische Spielbeobachtung – Testgüte des Videotrackings im Sports Performance Analyzer (SPA)

    Paier, Daniel; Schnittker, Reinhard; Reinecke, Kirsten; Wilhelm, Per; Preis, Robert; Weiß, Michael; Baumeister, Jochen

    Aus sportmedizinischer Sicht sind detaillierte Anforderungsprofile in komplexen Spielsportarten wichtig. Ein neu entwickeltes Videotrackingsystem mit synchroner Aufzeichnung physiologischer Daten (SPA) kann helfen, Bewegungsprofile zu analysieren. Um hiermit Anforderungsprofile verlässlich erheben zu können, ist das Testen auf Gütekriterien unerlässlich. Ziel der Untersuchung ist die Beurteilung der Komponente Videotracking hinsichtlich der Testgütekriterien Validität, Reliabilität und Objektivität. Methodik: 13 Probanden (22,5J ± 2,1; 180,3cm ± 10,5) absolvieren auf einem Handballfeld eine Testbatterie bestehend aus abgemessenen Laufwegen (Stand, Quadratlauf, Kreislauf) und durch Taktgeber bestimmte Geschwindigkeiten (Soll-Daten). Der Test wird von 2 mittig über jeder Spielfeldhälfte platzierten Kameras mit 30 fps aufgezeichnet. Die Spielerköpfe werden durch Trajektorien nachverfolgt und die Daten in Koordinaten (x; y) pro Bild gespeichert. Aus diesen Daten lassen sich Laufwege und -intensitäten errechnen (Ist-Daten). Die errechneten Ist-Daten werden mit den Solldaten deskriptiv auf Validität und prüfstatistisch auf Reliabilität und Objektivität geprüft. Ergebnisse: Standpositionen der Spieler werden mit durchschnittlichen Abweichungen von X=0,28m ± 0,47 und Y=0,14m ± 0,42 angegeben. Bei den Laufstrecken ermittelt das System für den Quadratlauf einen Fehler von ±10,4% (v=1m/s), ±6,81% (v=1,5m/s) und ±2,72% (v=2m/s) im Vergleich zu den Sollstrecken. Bei einem Kurvenlauf (r=4m) stellt das System die Laufstrecke mit einem Fehler von ±8,96% (v=1m/s), ±3,83% (v=1,5m/s) und ±2,02% (v=2m/s) dar. Das ergibt eine durchschnittliche Abweichung der tatsächlich gelaufenen Strecke von 5,79%. Bei Testwiederholung korrelieren die Ergebnisse beim Quadratlauf signifikant (r=0,867, p␣0.01 [1m/s]; r=0,838, p␣0.01 [1,5m/s]; r=0,921, p␣0.01 [2m/s]) und beim Kurvenlauf (r=0,778, p␣0.01 [1m/s]; r=0,687, p␣0.05 [1,5m/s] r=0,812, p␣0.01 [2m/s]). Bezüglich der Objektivität stellen sich die Ergebnisse der Korrelationen signifikant dar (p␣0.05). Schlussfolgerung: Die Untersuchung zeigt, dass die mit SPA ermittelten Daten für Feldversuche und sportartbezogene Anforderungsprofile als ausreichend valide, reliabel und objektiv bewertet werden können. Somit ist die Komponente Videotracking geeignet, um bei komplexen Spielsportarten verlässlich zu analysieren. Mit Hilfe der dazugehörigen physiologischen Parameter und leistungsdiagnostischen Daten kann dann eine Aussage über die individuelle Beanspruchung der Spieler getroffen werden.


    In: Deutsche Zeitschrift für Sportmedizin, Volume: 60, 2009.
  • Kim, J.-H.; Sam Ge, S.; Vadakkepat, P.; Jesse, Norbert; Al Mamun, A.; Puthusserypady, S.; Rückert, Ulrich; Sitte, Joaquin; Witkowski, Ulf; Nakatsu, R.; Braunl, Th.; Baltes, J.; Anderson, J.; Wong, C.-C.; Verner, I.; Ahlgren, D.:
    Progress in Robotics, Proceedings of the FIRA RoboWorld Congress 2009.
    In: Springer, 2009. »»

    book / id: 2144730

  • Monier, Emad; Wilhelm, Per; Rückert, Ulrich:
    A Computer Vision Based Tracking System for Indoor Team Sports.
    In: The fourth International Conference on Intelligent Computing and Information Systems, 2009. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2144805

    A Computer Vision Based Tracking System for Indoor Team Sports

    Monier, Emad; Wilhelm, Per; Rückert, Ulrich

    This paper presents a video tracking system for tracking players in indoor sports using two high quality digital cameras. The tracking algorithm is based on template matching technique taking into consideration closed world assumptions. The output of the system can be visualized interactively for convenient analysis of player movements. The implementation has been efficiently done as a software system that can be used by coaches and sport scientists.


    In: The fourth International Conference on Intelligent Computing and Information Systems, 2009.
  • Monier, Emad; Wilhelm, Per; Rückert, Ulrich:
    Template Matching Based Tracking of Players in Indoor Team Sports.
    In: Third ACM/IEEE International Conference on Distributed Smart Cameras (ICDSC 2009), 2009. »»
    Abstract

    conference paper / id: 2144817

    Template Matching Based Tracking of Players in Indoor Team Sports

    Monier, Emad; Wilhelm, Per; Rückert, Ulrich

    This paper presents a video tracking system for tracking players in indoor sports using two high quality digital cameras. The tracking algorithm is a based on template matching technique taking into consideration closed world assumptions. The output of the system can be visualized interactively for convenient analysis of player movements. The implementation has been efficiently done as a software system that can be used by coaches and sport scientists.


    In: Third ACM/IEEE International Conference on Distributed Smart Cameras (ICDSC 2009), 2009.
  • Paiz, Carlos; Hagemeyer, Jens; Pohl, Christopher; Porrmann, Mario; Rückert, Ulrich; Schulz, Bernd; Peters, Wilhelm; Böcker, Joachim:
    FPGA-Based Realization of Self-Optimizing Drive-Controllers.
    In: the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009), 2009. »»

    FPGA-Based Realization of Self-Optimizing Drive-Controllers

    Paiz, Carlos; Hagemeyer, Jens; Pohl, Christopher; Porrmann, Mario; Rückert, Ulrich; Schulz, Bernd; Peters, Wilhelm; Böcker, Joachim

    An FPGA (Field Programmable Gate Array) implementation and suitable power electronics can lead to a fast torque response in motion drive applications. However, when the controller parameters or its structure have to be adapted to internal and external varying conditions, e.g., when a selfoptimizing control system is pursued, a static implementation might not lead to the best utilization of reconfigurable resources. This contribution outlines the implementation of a self-optimizing system composed of several possible hardware and software realizations of controllers for a permanent magnet servo motor. How well a specific controller realization is suited to the current situation is evaluated based on control quality and realization effort (i.e., CPU time, reconfigurable area). A System-on-Chip architecture is presented, which enables an on-line exchange of FPGA- and CPU-based realizations of controllers to optimize resource utilization and control quality. It is shown that by using dynamic hardware reconfiguration, such self-optimizing controller can be implemented based on FPGA technology. Furthermore, the design-flow including self-developed tools is outlined. Experimental results show that the proposed scheme works satisfactory.


    In: the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009), 2009.
  • Amin, Safaa; Tanoto, Andry; Witkowski, Ulf; Abdel-Wahab, Mohammed:
    Effect of global position information in unknown world exploration - A case study using the Teleworkbench.
    In: Robotics and Autonomous Systems, Volume: 57, Elsevier BV, 2009. »»
    Abstract

    article / id: 2144874

    Effect of global position information in unknown world exploration - A case study using the Teleworkbench

    Amin, Safaa; Tanoto, Andry; Witkowski, Ulf; Abdel-Wahab, Mohammed

    This paper presents empirical results of the effect of the global position information on the performance of the modified local navigation algorithm (MLNA) for unknown world exploration. The results show that global position information enables the algorithm to maintain 100% success rate irrespective of initial robot position, movement speed, and environment complexity. Most mobile robot systems accrue an odometry error while moving, and hence need to use external sensors to recalibrate their position on an ongoing basis. We deal with position calibration to compensate the odometry error using the global position information provided by the Teleworkbench, which is a teleoperated platform and test bed for managing experiments using mini-robots. In this paper we demonstrate how we incorporate the global position information during and after the experiments.


    In: Robotics and Autonomous Systems, Volume: 57, Elsevier BV, 2009.
  • Kim, J.-H.; Sam Ge, S.; Vadakkepat, P.; Jesse, Norbert; Al Mamun, A.; Puthusserypady, S.; Rückert, Ulrich; Sitte, Joaquin; Witkowski, Ulf; Nakatsu, R.; Braunl, Th.; Baltes, J.; Anderson, J.; Wong, C.-C.; Verner, I.; Ahlgren, D.:
    Advances in Robotics, Proceedings of the FIRA RoboWorld Congress 2009.
    In: Volume: 5744, Springer, 2009. »»

    book / id: 2144898

  • Grassi, Paolo Roberto; Santambrogio, M.; Hagemeyer, Jens; Pohl, Christopher; Porrmann, Mario:
    SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09), 2009. »»

    conference paper / id: 2472686

  • Herath, Vijitha; Peveling, Ralf; Pfau, Timo; Adamczyk, Olaf; Hoffmann, Sebastian; Wördehoff, Christian; Porrmann, Mario; Noe, Reinhold:
    Cipset for a Coherent Polarization-Multiplexed QPSK Receiver.
    In: Proceedings of OFC/NFOEC 2009, 2009. »»
    Abstract

    conference paper / id: 2493834

    Cipset for a Coherent Polarization-Multiplexed QPSK Receiver

    Herath, Vijitha; Peveling, Ralf; Pfau, Timo; Adamczyk, Olaf; Hoffmann, Sebastian; Wördehoff, Christian; Porrmann, Mario; Noe, Reinhold

    Test results of the first modular receiver signal processor prototype for coherent polarization-multiplexed QPSK transmission are presented. The achieved BER at a data rate of 10 Gb/s is well below FEC threshold.


    In: Proceedings of OFC/NFOEC 2009, 2009.
  • Lütkemeier, Sven; Kaulmann, Tim; Rückert, Ulrich:
    A Sub-200mV 32bit ALU with 0.45pJ/instruction in 90nm CMOS.
    In: Semiconductor Conference Dresden, 2009. »»
    Abstract

    conference paper / id: 2289299

    A Sub-200mV 32bit ALU with 0.45pJ/instruction in 90nm CMOS

    Lütkemeier, Sven; Kaulmann, Tim; Rückert, Ulrich

    We have implemented a 32bit ALU operating at voltages from 115mV to 1V on a die area of 0.021mm² in 90nm bulk CMOS. The energy minimum of 0.45pJ/instruction is achieved at a supply voltage of 210mV with the ALUs operating at a clock frequency of 3MHz. A yield of 88.5% can be reported for a supply voltage of 200mV, and 75% for a supply voltage of 120mV without any body biasing applied. The ALUs have been implemented with an automated design flow and a custom standard cell library, optimized for sub-threshold operation.


    In: Semiconductor Conference Dresden, 2009.
  • Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich:
    Vision Module for Mini-robots Providing Optical Flow Processing for Obstacle Avoidance.
    In: Proceedings of the FIRA RoboWorld Congress 2009 on Advances in Robotics, Springer-Verlag, 2009. »»
    Abstract

    conference paper / id: 2289340

    Vision Module for Mini-robots Providing Optical Flow Processing for Obstacle Avoidance

    Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich

    This paper presents a flexible prototyping platform that can be efficiently used for vision systems of small mobile robots. The vision module has been integrated into the mini-robot “Khepera”. The module is utilized to realize optical flow algorithm for obstacle avoidance. The obstacles are detected from abrupt change of the normal flow vectors during operation. This technique is also inspired by visual perception of insects, which alert when an object suddenly appears nearby them. The optical flow algorithm implemented for this approach is Sum of Absolute Differences (SAD) algorithm. The SAD is programmed using the hardware description language (VHDL) efficiently utilizing the FPGA device that is the central processing device of the module. The 30x16 pixels used in SAD for block matching are computed in parallel by 16 pairs of pixels in each operation, which allows in real-time operation. Therefore, the mini-robot being equipped with our 2D vision module for the real-time image processing is able to drive autonomously without collision with obstacles, called ego-motion. The result also shows that the implementation can reduce the execution time compared to serial implementation and helps to reduce energy consumption.


    In: Proceedings of the FIRA RoboWorld Congress 2009 on Advances in Robotics, Springer-Verlag, 2009.
  • Liß, Christian; Porrmann, Mario; Rückert, Ulrich:
    InCyte ChipEstimator in Research and Education.
    In: CDNLive EMEA 2009, 2009. »»

    conference paper / id: 2144772

  • Neuwinger, Bernd; Witkowski, Ulf; Rückert, Ulrich:
    Ad-Hoc Communication and Localization System for Mobile Robots.
    In: Advances in Robotics, Volume: 5744/2009, Springer-Verlag, 2009. »»
    Abstract

    conference paper / id: 2144791

    Ad-Hoc Communication and Localization System for Mobile Robots

    Neuwinger, Bernd; Witkowski, Ulf; Rückert, Ulrich

    Robots exploring unknown territory cannot rely on fixed infrastructure for communication and localization purposes. Therefore an ad-hoc communication and localization system is required to provide such facilities. In this paper a solution for a radio based localization system is presented using a 2.4 GHz wireless radio transceiver based on Chirp Spread Spectrum (CSS) modulation, which allows distance measurements by evaluating the signal propagation delay. Using odometry data as additional information source a communication and positioning system is developed fulfilling ad-hoc demands.


    In: Advances in Robotics, Volume: 5744/2009, Springer-Verlag, 2009.
  • Hoffmann, Sebastian; El-Darawy, Mohamed; Pfau, Timo; Wördehoff, Christian; Peveling, Ralf; Rückert, Ulrich; Noe, Reinhold:
    Realtime Phase Tracking with Multiplier-Free Barycenter Approximation in Digital Synchronous QPSK Receiver for Coherent Detection.
    In: LEOS, Annual Meeting 2009, 2009. »»
    Abstract

    conference paper / id: 2144809

    Realtime Phase Tracking with Multiplier-Free Barycenter Approximation in Digital Synchronous QPSK Receiver for Coherent Detection

    Hoffmann, Sebastian; El-Darawy, Mohamed; Pfau, Timo; Wördehoff, Christian; Peveling, Ralf; Rückert, Ulrich; Noe, Reinhold

    A multiplier-free phase estimation algorithm for coherent QPSK detection is presented. The barycenter approach is modified by a selectivity mechanism that improves performance. In addition to recently published measurement results, theoretical derivations and simulation results are provided.


    In: LEOS, Annual Meeting 2009, 2009.
  • Jungeblut, Thorsten; Klassen, Dennis; Dreesen, Ralf; Porrmann, Mario; Thies, Michael; Rückert, Ulrich; Kastens, Uwe:
    Design Space Exploration for Next Generation Wireless Technologies (invited talk)..
    In: Proc. of the Electrical and Electronic Engineering for Communication Conference (EEEfCOM) 2009, 2009. »»

    conference paper / id: 2144830

  • Pohl, Christopher; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich:
    Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks.
    In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09), 2009. »»
    Abstract

    conference paper / id: 2144880

    Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks

    Pohl, Christopher; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich

    In this paper we present the RAPTOR family as an advanced modular platform for both FPGA-based rapid prototyping and hardware acceleration. Using modern FPGAs and high speed communication links, performance and flexibility of the approach will be shown by means of Kohonens selforganizing map algorithm. This highly parallel algorithm is partitioned onto several FPGAs in different system environments, such as to demonstrate the scalability and the flexibility of the proposed platforms.


    In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09), 2009.
  • Noe, Reinhold; Rückert, Ulrich; Hoffmann, Sebastian; Pfau, Timo; Peveling, Ralf:
    Realization of Digital Coherent Receivers.
    In: LEOS, Annual Meeting 2009, 2009. »»
    Abstract

    conference paper / id: 2144885

    Realization of Digital Coherent Receivers

    Noe, Reinhold; Rückert, Ulrich; Hoffmann, Sebastian; Pfau, Timo; Peveling, Ralf

    The hardware architecture of digital coherent optical receivers supporting >40 Gb/s data rates and general considerations about signal processing algorithms are presented as well as a chipset layout for a 40 Gb/s digital coherent polarization-multiplexed QPSK receiver.


    In: LEOS, Annual Meeting 2009, 2009.
  • Koester, Markus; Luk, Wayne; Hagemeyer, Jens; Porrmann, Mario:
    Design Optimizations to Improve Placeability of Partial Reconfiguration Modules.
    In: Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009), ACM Press, 2009. »»
    Fulltext (external) Abstract

    conference paper / id: 2472673

    Design Optimizations to Improve Placeability of Partial Reconfiguration Modules

    Koester, Markus; Luk, Wayne; Hagemeyer, Jens; Porrmann, Mario

    In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. This paper focuses on the relation between the design options of partial reconfiguration modules and their placement at run-time. For a set of dynamic system components, we propose a design method that optimizes the feasible positions of the resulting partial reconfiguration modules to minimize position overlaps. We introduce the concept of subregions, which guarantees the parallel execution of a certain number of partial reconfiguration modules for tiled reconfigurable systems. Experimental results, which are based on a Xilinx Virtex-4 implementation, show that at run-time the average number of available positions can be increased up to 6.4 times and the number of placement violations can be reduced up to 60.6%.


    In: Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009), ACM Press, 2009.
  • Porrmann, Mario; Hagemeyer, Jens; Romoth, Johannes; Strugholtz, Manuel:
    Rapid Prototyping of Next-Generation Multiprocessor SoCs.
    In: Proceedings of Semiconductor Conference Dresden, SCD 2009, 2009. »»

    conference paper / id: 2472678

  • Purnaprajna, Madhura; Pohl, Christopher; Porrmann, Mario; Rückert, Ulrich:
    Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'09, July 13-16, 2009, Las Vegas, Nevada, USA, 2009. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2144752

    Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing

    Purnaprajna, Madhura; Pohl, Christopher; Porrmann, Mario; Rückert, Ulrich

    Parallelism and adaptability are two distinct architectural design considerations in embedded processors. Multicore processors accelerate application execution on account of their inherent parallelism and run-time reconfiguration capabilities add adaptability during infield deployment. To benefit from both these features, a reconfigurable multiprocessor architecture


    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'09, July 13-16, 2009, Las Vegas, Nevada, USA, 2009.
  • Dreesen, Ralf; Jungeblut, Thorsten; Thies, Michael; Porrmann, Mario; Rückert, Ulrich; Kastens, Uwe:
    A Synchronization Method for Register Traces of Pipelined Processors.
    In: Proceedings of the International Embedded Systems Symposium 2009 (IESS '09), 2009. »»
    Fulltext (external) Abstract

    conference paper / id: 2144757

    A Synchronization Method for Register Traces of Pipelined Processors

    Dreesen, Ralf; Jungeblut, Thorsten; Thies, Michael; Porrmann, Mario; Rückert, Ulrich; Kastens, Uwe

    During a typical development process of an embedded application specific processor (ASIP), the architecture is implemented multiple times on different levels of abstractions. As a result of this redundant specification, certain inconsistencies may show up. For example, the implementation of an instruction in the simulator may differ from the HDL implementation. To detect such inconsistencies, we use register trace comparison. Our key contribution is a generic method for systematic trace synchronization. Therefore, we convert a micro-architectural trace into an architectural trace. This method considers pipeline hazards and non-uniform write latencies. To simplify the validation of a processor, we further have implemented an automatic validation environment that includes a tool which points the developer directly to erroneous instructions. The flow has been validated during the development of our CoreVA architecture for mobile applications.


    In: Proceedings of the International Embedded Systems Symposium 2009 (IESS '09), 2009.
  • Blesken, Matthias; Rückert, Ulrich; Steenken, Dominik; Witting, Katrin; Dellnitz, Michael:
    Multiobjective Optimization for Transistor Sizing of CMOS Logic Standard Cells Using Set-Oriented Numerical Techniques.
    In: NORCHIP 2009, 2009. »»
    Abstract

    conference publication / id: 2144776

    Multiobjective Optimization for Transistor Sizing of CMOS Logic Standard Cells Using Set-Oriented Numerical Techniques

    The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus on the resources directly. In this work transistor sizing is approached via an MOP and solved by set-oriented numerical techniques. A comparison of the Pareto optimal designs to elements of a commercial standard cell library indicates that for some gates the performance can even be significantly improved.


    In: NORCHIP 2009, 2009.
  • El-Darawy, Mohamed; Herath, Vijitha; Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Adamczyk, Olaf; Wördehoff, Christian; Noe, Reinhold; Rückert, Ulrich:
    Analysis of an ASIC-based Coherent Polarization-Multiplexed QPSK Receiver and Different Receiver Frontends.
    In: 10. ITG-Fachtagung "Photonische Netze", ITG/VDE, 2009. »»
    Fulltext (external) Abstract

    conference paper / id: 2144795

    Analysis of an ASIC-based Coherent Polarization-Multiplexed QPSK Receiver and Different Receiver Frontends

    El-Darawy, Mohamed; Herath, Vijitha; Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Adamczyk, Olaf; Wördehoff, Christian; Noe, Reinhold; Rückert, Ulrich

    In this paper we present the characterization results of an optical coherent quadrature phase shift keying (QPSK) receiver with an application-specific integrated circuit (ASIC) based backend unit. Additionally we investigate the performance of an integrated optical coherent receiver frontend (ICR) and compare it against a fiber-pigtailed 90deg optical hybrid. After characterization of the CMOS ASIC, we measure and analyze single polarization QPSK transmission at 2.5 Gbaud with different optical receiver frontend setups. Also we measure the polarization-multiplexed QPSK transmission and discuss the possible reasons for reduced sensitivity compared to the single-polarization transmission.


    In: 10. ITG-Fachtagung "Photonische Netze", ITG/VDE, 2009.
  • Wilhelm, Per; Monier, Emad; Thomas, Patrick; Rückert, Ulrich:
    SPA - A System for Analysis of Indoor Team Sports Using Video Tracking and Wireless Sensor Network.
    In: 6th International Symposium on Image and Signal Processing and Analysis (ISPA 2009), 2009. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2144865

    SPA - A System for Analysis of Indoor Team Sports Using Video Tracking and Wireless Sensor Network

    Wilhelm, Per; Monier, Emad; Thomas, Patrick; Rückert, Ulrich

    This paper presents a sport analysis system (SPA – Sport Performance Analyzer), consisting of a high resolution video system together with a wireless sensor network for collecting position data and physiological data of sport players during training or competition. The combination of the two data streams provides a new performance analysis and visualization solution for indoor team sports.


    In: 6th International Symposium on Image and Signal Processing and Analysis (ISPA 2009), 2009.
  • Paiz, Carlos; Pohl, Christopher; Radkowski, Rafael; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich:
    FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications.
    In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09), 2009. »»
    Abstract

    conference paper / id: 2144891

    FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications

    Paiz, Carlos; Pohl, Christopher; Radkowski, Rafael; Hagemeyer, Jens; Porrmann, Mario; Rückert, Ulrich

    This contribution presents a Hardware-in-the-Loop (HiL) design environment for FPGA-based systems. The presented tool-flow supports a two-stage verification process: A cycle-accurate HiL simulation using well-known simulation tools such as MATLAB/Simulink or Modelsim, and a real-time test using the target environment of the Design Under Test (DUT). The first stage allows an early verification of the DUT using a simulated environment, while the focus of the second stage is on monitoring internal states and I/Os of the DUT in operation, and on adjusting design parameters. All hardware and software interfaces required for both stages are generated individually and automatically by our tool-flow. The demo shows the benefits of using the presented HiL framework for applications targeting dynamic hardware reconfiguration. As an example, a twocontroller system for an inverted pendulum is presented, where either a real system or an FPGA-based model combined with an augmented reality 3D animation can be used.


    In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09), 2009.
  • Blesken, M.; Rückert, Ulrich; Steenken, D.; Witting, K.; Dellnitz, M.:
    Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques.
    In: NORCHIP, 2009, 2009. »»
    Abstract

    conference paper / id: 2286299

    Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques

    Blesken, M.; Rückert, Ulrich; Steenken, D.; Witting, K.; Dellnitz, M.

    The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus on the resources directly. In this work transistor sizing is approached via an MOP and solved by set-oriented numerical techniques. A comparison of the Pareto optimal designs to elements of a commercial standard cell library indicates that for some gates the performance can even be significantly improved.


    In: NORCHIP, 2009, 2009.
  • El-Habbal, Mohamed; Rückert, Ulrich; Witkowski, Ulf:
    Topology Control in Large-Scale High Dynamic Mobile Ad-Hoc Networks.
    In: Proceedings of the FIRA RoboWorld Congress 2009 on Advances in Robotics, Springer-Verlag, 2009. »»
    Abstract

    conference paper / id: 2289332

    Topology Control in Large-Scale High Dynamic Mobile Ad-Hoc Networks

    El-Habbal, Mohamed; Rückert, Ulrich; Witkowski, Ulf

    We present our contribution in projects related to ad-hoc networking using different routing protocols and hardware platforms, showing our results and new solutions regarding topology control and routing protocols. We mainly focus on our work in the GUARDIANS EU-project, where as a main disaster scenario a large industrial warehouse on fire is assumed. The paper presents the simulation results for the routing protocols ACR, DSR and EDSR, as well as the implementation of down-scaled demos for supporting the autonomous team of robots as well as the human squad team with robust communication coverage. Various hardware platforms were used in the demos for distance measurement, based on laser range finder and radio communication with time of flight analysis.


    In: Proceedings of the FIRA RoboWorld Congress 2009 on Advances in Robotics, Springer-Verlag, 2009.
  • Schnittker, Reinhard; Baumeister, Jochen; Paier, Daniel; Wilhelm, Per; Weiß, Michael:
    Leistungsvoraussetzungen und Anforderungsprofil im deutschen Profibasketball.
    In: Deutsche Zeitschrift für Sportmedizin, Volume: 60, 2009. »»
    Abstract

    article / id: 2295221

    Leistungsvoraussetzungen und Anforderungsprofil im deutschen Profibasketball

    Schnittker, Reinhard; Baumeister, Jochen; Paier, Daniel; Wilhelm, Per; Weiß, Michael

    Neben technisch-taktischen Ansprüchen bestimmen sowohl die Schnelligkeit als auch die Möglichkeit über mindestens 40 Minuten die Spielintensität aufrecht zu erhalten den Erfolg im Basketball. Nicht nur die im Training erarbeiteten konditionellen Merkmale, sondern auch die Umsetzung im Wettkampf schaffen dabei Anhaltspunkte für eine individuelle Beurteilung des Spielers. Methodik: Durch das Videoanalysesystem Sports Performance Analyser (SPA) mit zwei hochauflösenden Kameras zentral unter der Decke der Sporthalle können die Laufwege und - geschwindigkeiten der Spieler genau erfasst werden. Die Laufgeschwindigkeiten werden wie folgt kategorisiert: Standing (0-0,7 km/h), Walking (0,7-7,2), Jogging (7,2-14,4), Running (14,4-19,8), Sprinting (>19,8). Exemplarisch wird ein Spiel der BBL aus der Saison 2008/09 untersucht, wobei die Spieler der siegreichen Heimmannschaft analysiert werden. Des Weiteren werden die leistungsdiagnostischen Daten der Saisonvorbereitung vorgestellt. Ergebnisse: Im Bezug auf die Spielanalyse betrug die Einzellaufstrecke der fünf Spieler, die auf dem Feld standen, durchschnittlich 5923m (Standing 178m, Walking 2734m, Jogging 2029m, Running 740m, Sprinting 241m).Die Spieler mit wenig Einsatzzeit wiesen eine tendenziell höhere durchschnittliche Laufgeschwindigkeit auf(r=-0,597,p=0,069). Acht Spieler (198,4±6,7 cm), welche an beiden Ausdauerfeldstufentests teilnahmen, veränderten ihre 4mmol/l Schwelle im Laufe der Vorbereitung von 3,62±0,32 auf 3,73±0,34 m/s (p=0,099), wobei das Gewicht von 93,1±11,6 auf 91,4±12,0 kg sank (p=0,008). Die Herzfrequenz bei der Stufe 3,5 m/s reduzierte sich von 170,5±9,9 auf 160,8±8,7 (p=0,026). Weitere einmalig erhobene Daten von 6 Spielern stellen sich folgendermaßen dar: Sprint [s]: 5m: 1,04±0,04; 10m:1,78±0,4; 30m: 4,28±0,05; Sprung [cm]: Counter Movement Jump ohne Armeinsatz: 41,8±3,6; mit Armeinsatz: 48,3±4,2; Drop Jump: 36,1±2,8. Zusammenfassung: Die Center absolvierten eine etwas geringere Laufstrecke pro Zeit, wobei dieläuferische Anforderungsstruktur zwischen den Spielpositionen nicht stark varierte.Kürzer eingesetzte Spielerkompensierten dies mit höherer Laufintensität. Weitere Spielanalysen sind erforderlich um Entwicklungen derleistungsdiagnostischen Parametermit Veränderungen der Laufleistungen zu vergleichen.


    In: Deutsche Zeitschrift für Sportmedizin, Volume: 60, 2009.
  • Pohl, Christopher; Paiz, Carlos; Porrmann, Mario:
    vMAGIC - Automatic Code Generation for VHDL.
    In: International Journal of Reconfigurable Computing, Hindawi Publishing Corporation,, Volume: 2009, Hindawi Publishing Corporation, 2009. »»
    Fulltext (external) Abstract

    article / id: 2493628

    vMAGIC - Automatic Code Generation for VHDL

    Pohl, Christopher; Paiz, Carlos; Porrmann, Mario

    Automatic code generation is a standard method in software engineering, improving the code reliability as well as reducing the overall development time. In hardware engineering, automatic code generation is utilized within a number of development tools, the integrated code generation functionality, however, is not exposed to developers wishing to implement their own generators. In this paper, VHDL Manipulation and Generation Interface (vMAGIC), a Java library to read, manipulate, and write VHDL code is presented. The basic functionality as well as the designflow is described, stressing the advantages when designing with vMAGIC. Two real-world examples demonstrate the power of code generation in hardware engineering.


    In: International Journal of Reconfigurable Computing, Hindawi Publishing Corporation,, Volume: 2009, Hindawi Publishing Corporation, 2009.
  • Grassi, Paolo Roberto; Santambrogio, M.; Puttmann, Christoph; Pohl, Christopher; Porrmann, Mario:
    A High Level Methodology for Monitoring Network-on-Chips.
    In: Diagnostic Services in Network-on-Chips (DSNOC 2009), Workshop at Design, Automation and Test in Europe., 2009. »»

    conference paper / id: 2493870

  • Liß, Christian; Porrmann, Mario; Rückert, Ulrich:
    Early Exploration of Network Processor Architectures Using Cadence InCyte Chip Estimator.
    In: CDNLive EMEA 2009, 2009. »»

    conference paper / id: 2144782

  • Witkowski, Ulf; Sitte, Joaquin; Herbrechtsmeier, Stefan; Rückert, Ulrich:
    AMiRESot – A New Robot Soccer League with Autonomous Miniature Robots.
    In: Progress in Robotics. FIRA RoboWorld Congress 2009, Incheon, Korea, August 16-20, 2009. Proceedings, Volume: 44, FIRA RoboWorld Congress, Springer, 2009. »»
    Abstract

    conference paper / id: 2144821

    AMiRESot – A New Robot Soccer League with Autonomous Miniature Robots

    Witkowski, Ulf; Sitte, Joaquin; Herbrechtsmeier, Stefan; Rückert, Ulrich

    AMiRESot is a new robot soccer league that is played with small autonomous miniature robots. Team sizes are defined with one, two, and three robots per team. Special to the AMiRESot league are the fully autonomous behavior of the robots and their small size. For the matches, the rules mainly follow the FIFA laws with some modifications being useful for robot soccer. The new AMiRESot soccer robot is small in size (maximum 110 mm diameter) but a powerful vehicle, equipped with a differential drive system. For sensing, the robots in their basic configuration are equipped with active infrared sensors and a color image sensor. For information processing a powerful mobile processor and reconfigurable hardware resources (FPGA) are available. Due to the robot’s modular structure it can be easily extended by additional sensing and processing resources. This paper gives an overview of the AMiRESot rules and presents details of the new robot platform used for AMiRESot.


    In: Progress in Robotics. FIRA RoboWorld Congress 2009, Incheon, Korea, August 16-20, 2009. Proceedings, Volume: 44, FIRA RoboWorld Congress, Springer, 2009.
  • Herbrechtsmeier, Stefan; Witkowski, Ulf; Rückert, Ulrich:
    BeBot: A Modular Mobile Miniature Robot Platform Supporting Hardware Reconfiguration and Multi-standard Communication.
    In: Progress in Robotics, Communications in Computer and Information Science. Proceedings of the FIRA RoboWorld Congress 2009, Volume: 44, Springer, 2009. »»
    Abstract

    conference paper / id: 2144826

    BeBot: A Modular Mobile Miniature Robot Platform Supporting Hardware Reconfiguration and Multi-standard Communication

    Herbrechtsmeier, Stefan; Witkowski, Ulf; Rückert, Ulrich

    Mobile robots become more and more important in current research and education. Especially small ’on the table’ experiments attract interest, because they need no additional or special laboratory equipments. In this context platforms are desirable which are small, simple to access and relatively easy to program. An additional powerful information processing unit is advantageous to simplify the implementation of algorithm and the porting of software from desktop computers to the robot platform. In this paper we present a new versatile miniature robot that can be ideally used for research and education. The small size of the robot of about 9 cm edge length, its robust drive and its modular structure make the robot a general device for single and multi-robot experiments executed ’on the table’. For programming and evaluation the robot can be wirelessly connected via Bluetooth or WiFi. The operating system of the robot is based on the standard Linux kernel and the GNU C standard library. A player/stage model eases software development and testing.


    In: Progress in Robotics, Communications in Computer and Information Science. Proceedings of the FIRA RoboWorld Congress 2009, Volume: 44, Springer, 2009.
  • Tanoto, Andry; Rückert, Ulrich; Witkowski, Ulf; Tzafestas, Spyros G.:
    Teleworkbench: A Teleoperated Platform for Experiments in Multi-Robotics.
    In: Web-Based Control and Robotics Education, Volume: 38, Springer Verlag, 2009. »»
    Abstract

    book chapter / id: 2144838

    Teleworkbench: A Teleoperated Platform for Experiments in Multi-Robotics

    Tanoto, Andry; Rückert, Ulrich; Witkowski, Ulf

    Robot development is a highly complex and interdisciplinary process. It comprises several phases: design, implementation, as well as test and validation to name some of them. In test and validation, simulation is commonly used. However, experiments with real robots still have a very important role since simulations cannot accurately model the real environment and, as a result, produce inconclusive results [1]. Performing robotic experiments, however, is considerably tedious. It is a repetitive process consisting of several steps: setup, execution, data logging, monitoring, and analysis. Moreover, it also requires a lot of resources especially in the case of experiments in multi-robotics. We have designed a system that can ease the tasks of performing experiments with single or multi minirobots, called the Teleworkbench [2]. The aim of the system is to provide a standard environment in which algorithms and programs can be tested and validated using real robots. As they run in a standardized environment, benchmarking in robotics can be achieved. Also there are several reasons to choose minirobots: the small-size, low-complexity, and low-cost to name a few. Moreover, it is easy to scale up developed solutions for minirobots to larger platforms or to scale them down to micro-mechanical systems (MEMS).


    In: Web-Based Control and Robotics Education, Volume: 38, Springer Verlag, 2009.
  • Pfau, Timo; Peveling, Ralf; Herath, Vijitha; Hoffmann, Sebastian; Wördehoff, Christian; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold:
    Towards Real-Time Implementation of Coherent Optical Communication.
    In: Proceedings of OFC/NFOEC 2009, 2009. »»
    Abstract

    conference paper / id: 2493855

    Towards Real-Time Implementation of Coherent Optical Communication

    Pfau, Timo; Peveling, Ralf; Herath, Vijitha; Hoffmann, Sebastian; Wördehoff, Christian; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold

    We outline the hardware architecture of coherent optical receivers supporting >40 Gb/s data rates and extract constraints for compatible signal processing algorithms. Additionally a chipset layout for a 40 Gb/s digital coherent polarization-multiplexed QPSK receiver is presented.


    In: Proceedings of OFC/NFOEC 2009, 2009.
  • Pohl, Christopher; Fuest, Ralf; Porrmann, Mario:
    Manageable Dynamic Reconfiguration with EVE – Extendable VHDL Editor.
    In: Design Automation and Test in Europe (DATE), University Booth, 2009. »»
    Fulltext (external) Abstract

    conference paper / id: 2494485

    Manageable Dynamic Reconfiguration with EVE – Extendable VHDL Editor

    Pohl, Christopher; Fuest, Ralf; Porrmann, Mario

    Dynamic reconfiguration of FPGAs is a promising approach for saving resources, thus becoming attractive for industrial applications. In this paper we present a complete tool flow which enables users to create dynamically reconfigurable systems without in depth knowledge of the underlying hardware and methodologies.


    In: Design Automation and Test in Europe (DATE), University Booth, 2009.
  • Grassi, Paolo Roberto; Pohl, Christopher; Porrmann, Mario:
    Reconfiguration Viewer.
    In: Design Automation and Test in Europe, DATE University Booth, 2009. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2144724

    Reconfiguration Viewer

    Grassi, Paolo Roberto; Pohl, Christopher; Porrmann, Mario

    The proposed approach allows debugging of partial dynamic reconfiguration. It shows where and when FPGA areas are reconfigured at runtime.


    In: Design Automation and Test in Europe, DATE University Booth, 2009.
  • Loeb, Hans-Peter; Liß, Christian; Sauer, Christian; Rückert, Ulrich:
    UMAC – A Universal MAC Architecture for Heterogeneous Home Networks.
    In: The International Workshop on Wireless and Optical Networks (WI-OPT 2009), Workshop at International Conference on Ultra Modern Telecommunications (ICUMT-2009), 2009. »»
    Abstract

    conference paper / id: 2144786

    UMAC – A Universal MAC Architecture for Heterogeneous Home Networks

    Loeb, Hans-Peter; Liß, Christian; Sauer, Christian; Rückert, Ulrich

    In-Home networks are becoming increasingly heterogeneous, as more wireless, optical, and wired communication technologies become available. The heterogeneity favors flexible computing platforms for the network nodes, like the Universal MAC (UMAC) introduced in this paper. Its architecture is illustrated together with its integral programming model for Media Access Control processing. The paper also addresses the reference applications of the UMAC, namely IEEE 802.11n MAC processing, and the InterMAC, a new sub-layer designed for heterogeneous home networks. The InterMAC is able to manage and exploit the heterogeneity. The paper concludes with the description of a Wireless LAN prototype that uses both MAC applications to implement a node of the future home network.


    In: The International Workshop on Wireless and Optical Networks (WI-OPT 2009), Workshop at International Conference on Ultra Modern Telecommunications (ICUMT-2009), 2009.
  • Hoffmann, Sebastian; Herath, Vijitha; El-Darawy, Mohamed; Pfau, Timo; Wördehoff, Christian; Peveling, Ralf; Rückert, Ulrich; Noe, Reinhold:
    Multiplier-Free Realtime Phase Tracking in Digital Synchronous QPSK, Receiver for Coherent Optical Detection.
    In: ICIIS2009, CIE3-1, 28.-31. Dec. 2009, University of Perydenia, Sri Lanka, 2009. »»
    Abstract

    conference paper / id: 2144856

    Multiplier-Free Realtime Phase Tracking in Digital Synchronous QPSK, Receiver for Coherent Optical Detection

    Hoffmann, Sebastian; Herath, Vijitha; El-Darawy, Mohamed; Pfau, Timo; Wördehoff, Christian; Peveling, Ralf; Rückert, Ulrich; Noe, Reinhold

    A multiplier-free phase estimation algorithm based on the barycentre approach for coherent QPSK detection is presented. A selectivity mechanism was developed that significantly improved its performance. In addition to recently published measurement results, theoretical background and new simulation results are presented.


    In: ICIIS2009, CIE3-1, 28.-31. Dec. 2009, University of Perydenia, Sri Lanka, 2009.
  • Purnaprajna, Madhura; Porrmann, Mario; Rückert, Ulrich:
    Run-time reconfigurability in embedded multiprocessors.
    In: ACM SIGARCH Computer Architecture News, Volume: 37, Association for Computing Machinery (ACM), 2009. »»
    Fulltext (external) Abstract

    article / id: 2144870

    Run-time reconfigurability in embedded multiprocessors

    Purnaprajna, Madhura; Porrmann, Mario; Rückert, Ulrich

    To meet application-specific performance demands, architectures are predominantly redesigned and customised. Every architectural change results in huge overheads in design, verification, and fabrication, which together result in prolonged time-to-market. As an alternative, configurable architectures provide easy adaptability to different application domains in place of costly redesigns. To deal with application changes and custom requirements, a method of configuring and reusing the basic building blocks within processors is developed. Additionally, this enables co-operative multiprocessing. In this paper, a runtime reconfiguration mechanism for embedded multiprocessor architectures is proposed as a method to introduce customisations in the post-fabrication phase. A method of application description in conjunction with a flexible reconfigurable multiprocessor template is presented. Finally, the costs and benefits of this approach are analysed for computationally intensive algorithms used in digital signal processing. The impact of applicationspecific characteristics on execution time, power consumption, and total energy dissipation are analysed.


    In: ACM SIGARCH Computer Architecture News, Volume: 37, Association for Computing Machinery (ACM), 2009.
  • Noe, R.; Rückert, Ulrich; Hoffmann, S.; Peveling, R.; Pfau, T.; El-Darawy, M.; Al-Bermani, A.:
    Real-time implementation of digital coherent detection.
    In: Optical Communication, 2009. ECOC '09. 35th European Conference on, 2009. »»
    Fulltext (external) Abstract

    conference paper / id: 2285840

    Real-time implementation of digital coherent detection

    Noe, R.; Rückert, Ulrich; Hoffmann, S.; Peveling, R.; Pfau, T.; El-Darawy, M.; Al-Bermani, A.

    The implementation of algorithms for coherent detection of advanced modulation formats imposes constraints. A hardware-efficient phase estimator is presented, and measurement results with a CMOS receiver chip designed for 40 Gb/s digital coherent polarization-multiplexed QPSK.


    In: Optical Communication, 2009. ECOC '09. 35th European Conference on, 2009.
  • Porrmann, Mario; Purnaprajna, Madhura; Puttmann, Christoph:
    Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance.
    In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009), 2009. »»
    Abstract

    conference paper / id: 2493880

    Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance

    Porrmann, Mario; Purnaprajna, Madhura; Puttmann, Christoph

    A dynamically reconfigurable on-chip multiprocessor architecture will be presented, which can be adapted to changing application demands and to faults detected at runtime. The scalable architecture comprises lightweight embedded RISC processors that are interconnected by a hierarchical network-on-chip (NoC). Reconfigurability is integrated into the processors as well as into the NoC with minimal area and performance overhead. Adaptability of the architecture relies on a self-optimizing reconfiguration of the MPSoC at run-time. The resource-efficiency of the proposed architecture is analyzed based on FPGA and ASIC prototypes.


    In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009), 2009.
2008
  • Puttmann, Christoph; Shokrollahi, Jamshid; Porrmann, Mario; Rückert, Ulrich:
    Hardware Accelerators for Elliptic Curve Cryptography.
    In: Advances in Radio Science, Volume: 6, 2008. »»

    Hardware Accelerators for Elliptic Curve Cryptography

    Puttmann, Christoph; Shokrollahi, Jamshid; Porrmann, Mario; Rückert, Ulrich

    In this paper we explore different hardware accelerators for cryptography based on elliptic curves. Furthermore, we present a hierarchical multiprocessor system-onchip (MPSoC) platform that can be used for fast integration and evaluation of novel hardware accelerators. In respect of two application scenarios the hardware accelerators are coupled at different hierarchy levels of the MPSoC platform. The whole system is implemented in a state of the art 65 nm standard cell technology. Moreover, an FPGA-based rapid prototyping system for fast system verification is presented. Finally, a metric to analyze the resource efficiency by means of chip area, execution time and energy consumption is introduced.


    In: Advances in Radio Science, Volume: 6, 2008.
  • Ebied, Hala; Witkowski, Ulf; Rückert, Ulrich:
    Visual Landmarks Based on Self-localization of Mobile Robot Using an Alternative Geometric Triangulation Algorithm.
    In: The 5th International Conference on Computational Intelligence, Robotics and Autonomous Systems (CIRAS),19-21 June-2008, Linz, Austria., 2008. »»

    conference paper / id: 2289199

  • Amin, Safaa; Tanoto, Andry; Witkowski, Ulf; Rückert, Ulrich; Abdel-Wahab, Mohammed:
    Effect of Global Position Information in Unknown World Exploration – A Case Study using the Teleworkbench.
    In: IEEE Proceedings of the 5th International Conference on Computational Intelligence, Robotics and Autonomous System (CIRAS 2008), June 19 – 21, Linz, Austria, 2008. »»
    Abstract

    conference paper / id: 2289221

    Effect of Global Position Information in Unknown World Exploration – A Case Study using the Teleworkbench

    Amin, Safaa; Tanoto, Andry; Witkowski, Ulf; Rückert, Ulrich; Abdel-Wahab, Mohammed

    This paper presents empirical results of the effect of the global position information on the performance of the modified local navigation algorithm (MLNA) for unknown world exploration. The results show that global position information enables the algorithm to maintain 100% success rate irrespective of initial robot position, movement speed, and environment complexity. Most mobile robot systems accrue an odometry error while moving, and hence need to use external sensors to recalibrate their position on an ongoing basis. We deal with position calibration to compensate the odometry error using the global position information provided by the Teleworkbench, which is a teleoperated platform and test bed for managing experiments using mini-robots. In this paper we demonstrate how we incorporate the global position information during and after the experiments.


    In: IEEE Proceedings of the 5th International Conference on Computational Intelligence, Robotics and Autonomous System (CIRAS 2008), June 19 – 21, Linz, Austria, 2008.
  • Hagemeyer, Jens; Koester, Markus; Porrmann, Mario:
    Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures.
    In: 1. GI/ITG KuVS Fachgespräch Virtualisierung, Heinz Nixdorf Institut, Universität Paderborn, 2008. »»

    conference paper / id: 2472725

  • Hoffmann, Sebastian; Pfau, Timo; Adamczyk, Olaf; Wördehoff, Christian; Peveling, Ralf; Porrmann, Mario; Noe, Reinhold:
    Frequency Estimation and Compensation for Coherent QPSK Transmission with DFB Lasers.
    In: Proc. OSA Topical Meeting Coherent Optical Technologies and Applications (COTA), 2008. »»
    Fulltext (external) Abstract

    conference paper / id: 2493966

    Frequency Estimation and Compensation for Coherent QPSK Transmission with DFB Lasers

    Hoffmann, Sebastian; Pfau, Timo; Adamczyk, Olaf; Wördehoff, Christian; Peveling, Ralf; Porrmann, Mario; Noe, Reinhold

    We present a hardware-efficient combined frequency and phase estimator. It is capable of tracking phase noise of 10 GBaud optical QPSK transmission systems with DFB lasers and frequency mismatch up to 0.8 GHz.


    In: Proc. OSA Topical Meeting Coherent Optical Technologies and Applications (COTA), 2008.
  • Pfau, Timo; El-Darawy, Mohamed; Wördehoff, Christian; Peveling, Ralf; Hoffmann, Sebastian; Koch, Benjamin; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold:
    32-krad/s Polarization and 3-dB PDL Tracking in a Realtime Digital Coherent Polarization-Multiplexed QPSK Receiver.
    In: Proceedings of the 2008 IEEE-LEOS Summer Topical Meetings, 2008. »»
    Abstract

    conference paper / id: 2494096

    32-krad/s Polarization and 3-dB PDL Tracking in a Realtime Digital Coherent Polarization-Multiplexed QPSK Receiver

    Pfau, Timo; El-Darawy, Mohamed; Wördehoff, Christian; Peveling, Ralf; Hoffmann, Sebastian; Koch, Benjamin; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold

    The tolerance against fast polarization changes and PDL of a digital coherent QPSK receiver is determined in a 2.8 Gb/s realtime polarization-multiplexed transmission experiment. The sensitivity penalty for polarization changes with a speed of 32 krad/s on the Poincare sphere is 0.5 dB.


    In: Proceedings of the 2008 IEEE-LEOS Summer Topical Meetings, 2008.
  • Jungeblut, Thorsten; Grünewald, Matthias; Porrmann, Mario; Rückert, Ulrich:
    Realtime multiprocessor for mobile ad hoc networks.
    In: Advances in Radio Science, Volume: 6, 2008. »»

    Realtime multiprocessor for mobile ad hoc networks

    Jungeblut, Thorsten; Grünewald, Matthias; Porrmann, Mario; Rückert, Ulrich

    This paper introduces a real-time Multiprocessor System-On-Chip (MPSoC) for low power wireless applications. The multiprocessor is based on eight 32bit RISC processors that are connected via an Network-On-Chip (NoC). The NoC follows a novel approach with guaranteed bandwidth to the application that meets hard realtime requirements. At a clock frequency of 100MHz the total power consumption of the MPSoC that has been fabricated in 180 nm UMC standard cell technology is 772mW.


    In: Advances in Radio Science, Volume: 6, 2008.
  • Witkowski, Ulf; Herbrechtsmeier, Stefan; El Habbal, Mohamed Ahmed Mostafa; Rückert, Ulrich:
    Powerful Miniature Robot for Research and Education.
    In: IEEE Proceedings of the, 5th International Conference on Computational Intelligence, Robotics and Autonomous System (CIRAS 2008), June 19 – 21, Linz, Austria, 2008. »»

    conference paper / id: 2289244

  • von zur Gathen, J.; Rückert, Ulrich:
    Abschlußbericht des DFG-Projektes: Ressourceneffiziente Hardware-Software-Kombinationen für Kryptographie mit elliptischen Kurven.
    In: Heinz Nixdorf Institut, Universität Paderborn, 2008. »»

    report / id: 2285797

  • Witkowski, U.; Monier, E.; Rückert, Ulrich; El Ghoul, S.; El-Ghoniemy, M.S.; Wahab, M.S.A.; Fouad, A.; Hussein, A.; Kamal, A.; Abdel-Meniem, M.; El Khair, W.A.:
    An automated platform for minirobots experiments.
    In: Control, Automation, Robotics and Vision, 2008. ICARCV 2008. 10th International Conference on, 2008. »»
    Abstract

    conference paper / id: 2285920

    An automated platform for minirobots experiments

    Witkowski, U.; Monier, E.; Rückert, Ulrich; El Ghoul, S.; El-Ghoniemy, M.S.; Wahab, M.S.A.; Fouad, A.; Hussein, A.; Kamal, A.; Abdel-Meniem, M.; El Khair, W.A.

    In this paper, a platform for managing and providing remote access to robots was developed and constructed. The system helps to schedule, perform and analyze experiments using minirobots. A solution for recharging the robots automatically has been included in the system in order to save the time needed for manual recharging. The system can automatically interrupt the experiments, charge robots and then resume experiments. To reach this level of autonomy, a positioning system, path planning technique along with video streaming have been developed and implemented.


    In: Control, Automation, Robotics and Vision, 2008. ICARCV 2008. 10th International Conference on, 2008.
  • El-Darawy, Mohamed; Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Wördehoff, Christian; Koch, Benjamin; Porrmann, Mario; Adamczyk, Olaf; Noe, Reinhold:
    Fast Adaptive Polarization and PDL Tracking in a Real-Time FPGA-Based Coherent PolDM-QPSK Receiver.
    In: IEEE Photonics Technology Letters, Volume: 20, 2008. »»
    Abstract

    article / id: 2493648

    Fast Adaptive Polarization and PDL Tracking in a Real-Time FPGA-Based Coherent PolDM-QPSK Receiver

    El-Darawy, Mohamed; Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Wördehoff, Christian; Koch, Benjamin; Porrmann, Mario; Adamczyk, Olaf; Noe, Reinhold

    Fast polarization changes of 40 krad/s and 6-dB polarization-dependent loss (PDL) are tracked in a 2.8-Gb/s real-time coherent quadrature phase-shift keying receiver. The tolerance against fast polarization changes and PDL is measured for different polarization control time constants. The sensitivity penalty of the receiver at a polarization change speed of 40 krad/s is 0.7 dB at bit-error rate (BER) of 1times 10-3, with a BER floor of 6.1times10-7. With an additional PDL of 6 dB, these figures become 1.7 dB and 9.6 times 10-6, respectively.


    In: IEEE Photonics Technology Letters, Volume: 20, 2008.
  • Hoffmann, Sebastian; Bhandare, Suhas; Pfau, Timo; Adamczyk, Olaf; Wördehoff, Christian; Peveling, Ralf; Porrmann, Mario; Noe, Reinhold:
    Frequency and Phase Estimation for Coherent QPSK Transmission With Unlocked DFB Lasers.
    In: IEEE Photonics Technology Letters, Volume: 20, 2008. »»
    Abstract

    article / id: 2493667

    Frequency and Phase Estimation for Coherent QPSK Transmission With Unlocked DFB Lasers

    Hoffmann, Sebastian; Bhandare, Suhas; Pfau, Timo; Adamczyk, Olaf; Wördehoff, Christian; Peveling, Ralf; Porrmann, Mario; Noe, Reinhold

    This letter presents a hardware-efficient frequency estimator and an advanced phase estimation algorithm capable of tracking the phase noise of a 10-GBaud optical quadrature phase-shift-keying transmission system with standard distributed-feedback lasers in the presence of a frequency mismatch up to 1.2 GHz. This algorithm allows us to implement a digital coherent receiver without an analog frequency control circuit.


    In: IEEE Photonics Technology Letters, Volume: 20, 2008.
  • Münch, Eckehard; Gambuzza, Alfonso; Paiz, Carlos; Pohl, Christopher; Porrmann, Mario:
    FPGA-in-the-Loop Simulations with CAMEL-View.
    In: Self-optimizing Mechatronic Systems: Design the Future, 7th International Heinz Nixdorf Symposium., 2008. »»

    conference paper / id: 2493890

  • Puttmann, Christoph; Shokrollahi, Jamshid; Porrmann, Mario:
    Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography.
    In: Proceedings of the 5th Internation Conference on Information Technology: New Generations, ITNG 2008, 2008. »»
    Abstract

    conference paper / id: 2493939

    Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography

    Puttmann, Christoph; Shokrollahi, Jamshid; Porrmann, Mario

    In this paper we focus on the hardware acceleration of cryptographic algorithms by using instruction set extensions. Therefore, a holistic methodology for automated evaluation of instruction set extensions is presented. We propose a two-stage framework for analyzing the resource efficiency of extending an instruction set. With emphasis to elliptic curve cryptography, several instruction set extensions are implemented for a 32-bit RISC microprocessor and synthesized in a state of the art 65 nm low power standard cell CMOS technology. The achieved performance improvement is analyzed in respect to the hardware costs in terms of chip area and power consumption.


    In: Proceedings of the 5th Internation Conference on Information Technology: New Generations, ITNG 2008, 2008.
  • Pohl, Christopher; Paiz, Carlos; Porrmann, Mario:
    vMAGIC – VHDL Manipulation and Automation for Reliable System Development.
    In: Proceedings of the 3rd International Workshop on Reconfigurable Computing Education (on CD), 2008. »»

    conference paper / id: 2493960

  • El-Darawy, Mohamed; Pfau, Timo; Wördehoff, Christian; Koch, Benjamin; Hoffmann, Sebastian; Peveling, Ralf; Porrmann, Mario; Noe, Reinhold:
    Realtime 40 krad/s Polarization Tracking with 6 dB PDL in Digital Synchronous Polarization-Multiplexed QPSK Receiver.
    In: Proceedings of European Conference on Optical Communication (ECOC), 2008. »»
    Abstract

    conference paper / id: 2494141

    Realtime 40 krad/s Polarization Tracking with 6 dB PDL in Digital Synchronous Polarization-Multiplexed QPSK Receiver

    El-Darawy, Mohamed; Pfau, Timo; Wördehoff, Christian; Koch, Benjamin; Hoffmann, Sebastian; Peveling, Ralf; Porrmann, Mario; Noe, Reinhold

    Fast polarization changes of 40 krad/s (and 6 dB PDL) are tracked in a 2.8 Gb/s realtime coherent QPSK receiver with 0.7 dB (2.4 dB) sensitivity degradation.


    In: Proceedings of European Conference on Optical Communication (ECOC), 2008.
  • Witkowski, Ulf; Herbrechtsmeier, Stefan; Tanoto, Andry; El Habbal, Mohamed Ahmed Mostafa; Penders, Jacques; Alboul, Lyuba; Gancet, J.:
    Self-Optimizing Human-Robot Systems for Search and Rescue in Disaster Scenarios.
    In: Proceedings of the 7th International Heinz Nixdorf Symposium, 2008. »»

    Self-Optimizing Human-Robot Systems for Search and Rescue in Disaster Scenarios

    Witkowski, Ulf; Herbrechtsmeier, Stefan; Tanoto, Andry; El Habbal, Mohamed Ahmed Mostafa; Penders, Jacques; Alboul, Lyuba; Gancet, J.

    The increasing capabilities of robot systems enable new fields of practical applica- tions for individual robots as well as multi-robot systems. But for some applica- tion scenarios like a fire or earthquake disaster current robots are still too limited to act fully autonomously in the disaster area. To overcome these limitations we consider a heterogeneous team of humans and robots complementing each other. Core application considered in this paper is a large burning warehouse with smoke making it difficult for fire fighters to search the building and to orientate them- selves inside the warehouse. Therefore, an assisting team of robots is surrounding the fire fighters searching the proximity, providing orientation data, and establish- ing a wireless communication infrastructure on a basis of a mobile ad-hoc net- work. The adaptation of the robots is achieved by applying principles of self- optimization on different levels of the human-robot system. In this paper, we are considering self-optimization inside an individual robot to optimize its behaviour, within a group of robots, and in the entire system compris- ing of robots and humans. The focus of the optimization is the distribution of ro- bots by applying swarming behaviour for forming a mobile ad-hoc communica- tion network and performing map building.


    In: Proceedings of the 7th International Heinz Nixdorf Symposium, 2008.
  • Noe, R.; Rückert, Ulrich:
    Abschlußbericht zum EU-Projekt: synQPSK.
    In: Heinz Nixdorf Institut, Universität Paderborn, 2008. »»

    report / id: 2285789

  • Jungeblut, Thorsten; Dreesen, Ralf; Porrmann, Mario; Rückert, Ulrich; Hachmann, Ulrich:
    Design Space Exploration for Resource Efficient VLIW-Processors.
    In: University Booth of the Design, Automation and Test in Europe (DATE) conference, 2008. »»
    Abstract

    conference paper / id: 2289205

    Design Space Exploration for Resource Efficient VLIW-Processors

    Jungeblut, Thorsten; Dreesen, Ralf; Porrmann, Mario; Rückert, Ulrich; Hachmann, Ulrich

    This demonstrator shows our general purpose VLIWprocessor for applications on mobile phones. Four arithmetical logical units can process scalar or SIMD instructions in parallel. The system is designed for 300 MHz and achieves a performance of 1.2 GIPS or 2.4 GVOPS. Key component of our design flow is the processor specification language UPSLA.


    In: University Booth of the Design, Automation and Test in Europe (DATE) conference, 2008.
  • Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich:
    A Biologically-Inspired and Resource-Efficient Vision System using Mobile Mini-Robots for Obstacle Avoidance.
    In: 2008. »»
    Abstract

    conference publication / id: 2289231

    A Biologically-Inspired and Resource-Efficient Vision System using Mobile Mini-Robots for Obstacle Avoidance

    This paper describes a resource-efficient vision system for the mini-robot ”Khepera”. It is implemented to perform a fundamental approach of robotic navigation, which is obstacle detection by using an optical flow algorithm. This is inspired by visual perception of insects. The optical flow field is evaluated by implementing the sum of absolute differences (SAD) operation of block matching while the mobile mini-robot moves on texture plane. The SAD is realized in an additional processing module based on a Field Programmable Gate Array (FPGA) solution which can perform various tasks in parallel; for example, image processing, camera control and symbolic protocol transmission to the mini-robot. As a result, the Khepera equipped with 2D camera and the additional module is able to autonomously move avoiding collisions with obstacles, called ego-motion. The 30X16 SAD operation is processed by computing 16 pairs of pixels in each operation, which accomplishes the real-time approach. The proposed implementation reduces processing time and power consumption


    In: 2008.
  • Griese, Björn; Brinkmann, André; Porrmann, Mario:
    SelfS – A Real-Time Protocol for Virtual Ring Topologies.
    In: Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS '08), on CD, 2008. »»
    Abstract

    conference paper / id: 2493945

    SelfS – A Real-Time Protocol for Virtual Ring Topologies

    Griese, Björn; Brinkmann, André; Porrmann, Mario

    Real-time automation systems have evolved from centrally controlled sensor-actor systems to complex distributed computing systems. Therefore, the communication system becomes a crucial component that strongly influences performance. In this paper we present a simple distributed communication protocol that meets hard real-time constraints without requiring complex synchronization mechanisms. An advantage of the distributed protocol is that network planning can be reduced to a minimum. The protocol is based on virtual rings and can be easily embedded into arbitrary network topologies. Besides a detailed evaluation and analysis of the protocol, the paper includes lower bounds on jitter and performance for arbitrary communication patterns.


    In: Proceedings of the 16th International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS '08), on CD, 2008.
  • Purnaprajna, M.; Porrmann, Mario:
    Run-time Reconfigurable Multiprocessors.
    In: Proceedings of the 22nd International Parallel and Distributed Processing Symposium (IPDPS 2008), PhD Forum, 2008. »»
    Abstract

    conference paper / id: 2493957

    Run-time Reconfigurable Multiprocessors

    Purnaprajna, M.; Porrmann, Mario

    Architectural rigidity restricts a multiprocessor to a given application domain, demanding a redesign for every application. In this research we propose to merge a set of heterogeneous architectural diversities into a single architectural template. The concept is to introduce application-specific customization via a single cycle, area-efficient run-time reconfiguration. The method proposed is independent of the type of the individual processors. Experimental results on a diverse set applications show speedups in the range of 3-11 for a 4-processor cluster and additional energy savings of 17-60% on account of reconfiguration


    In: Proceedings of the 22nd International Parallel and Distributed Processing Symposium (IPDPS 2008), PhD Forum, 2008.
  • Purnaprajna, M.; Porrmann, Mario:
    Run-time Reconfigurable Cluster of Processors.
    In: Proceedings of 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, IEEE Computer Society, 2008. »»
    Fulltext (external) Abstract

    conference paper / id: 2494157

    Run-time Reconfigurable Cluster of Processors

    Purnaprajna, M.; Porrmann, Mario

    High performance requirements often necessitate redesigns for every new application, resulting in long time-tomarket. Every architectural change involves costs in terms of hardware design, verification and fabrication. As an alternative, architectural flexibility provides easy adaptability to different application domains in order to avoid the high cost of redesigns. Hence, a method of reusing the basic building blocks within processors to enable co-operative multiprocessing is proposed. Runtime reconfiguration is used as a method for application-specific customisation. Here, a method of application description in conjunction with a flexible multiprocessor template is proposed. Finally, the costs and benefits of this approach are analysed for a computationally intensive algorithm in terms of execution time and power consumption. The impact of variations in applicationspecific characteristics on the proposed architecture, are also analysed.


    In: Proceedings of 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, IEEE Computer Society, 2008.
  • Amin, Safaa; Tanoto, Andry; Witkowski, Ulf; Rückert, Ulrich; Abdel-Wahaab, Mohammad:
    Modified Local Navigation Strategy for Un-known Environment Exploration.
    In: 5th IEEE International Conference on Informatics in Control, Automation and Robotics, 2008. »»

    conference paper / id: 2289189

  • Wilhelm, Per; Monier, Emad; Xu, Feng; Witkowski, Ulf:
    Analysis of Indoor Team Sports Using Video Tracking and Wireless Sensor Network.
    In: World Congress of Performance Analysis of Sport VIII, 2008. »»

    Analysis of Indoor Team Sports Using Video Tracking and Wireless Sensor Network

    Wilhelm, Per; Monier, Emad; Xu, Feng; Witkowski, Ulf

    Our analysis system, consisting of a high resolution video system together with a wireless sensor network, is used for collecting position and physiologi- cal data of sport players during training or competition. The combination of the two data streams provides a new type of performance analysis and visu- alisation solution for indoor team sports.


    In: World Congress of Performance Analysis of Sport VIII, 2008.
  • Adelt, P.; Donoth, J.; Gausemeier, J.; Geisler, J.; Henkler, S.; Kahl, S.; Klöpper, B.; Krupp, A.; Münch, E.; Oberthür, S.; Paiz, C.; Podlogar, H.; Porrmann, Mario; Radkowski, R.; Schulz, C.; Schulz, A.; Schulz, B.; Vöcking, H.; Witkowski, U.; Witting, K.; Znamenshchykov, O.:
    Selbstoptimierende Systeme des Maschinenbaus – Definitionen, Anwendungen, Konzepte..
    In: Volume: Band 234, HNI-Verlagsschriftenreihe, 2008. »»

    book / id: 2493583

  • Pfau, Timo; Hoffmann, Sebastian; Adamczyk, Olaf; Peveling, Ralf; Herath, Vijitha; Porrmann, Mario; Noe, Reinhold:
    Coherent optical communication: Towards realtime systems at 40 Gbit/s and beyond.
    In: Optics Express, Volume: 16, 2008. »»
    Abstract

    article / id: 2493684

    Coherent optical communication: Towards realtime systems at 40 Gbit/s and beyond

    Pfau, Timo; Hoffmann, Sebastian; Adamczyk, Olaf; Peveling, Ralf; Herath, Vijitha; Porrmann, Mario; Noe, Reinhold

    Coherent optical communication systems promise superior performance, but their realization in real time also poses big technical challenges. After an introduction the potential of coherent optical transmission systems is shown as manifested in offline experiments. Then we present key components that are necessary to realize these systems in real time. We review recent achievements in realtime coherent communication and finally present the results of a realtime QPSK transmission system with a 3×3 coupler in the receiver. The achieved BER at a data rate of 1.4 Gbit/s is well below the FEC threshold.


    In: Optics Express, Volume: 16, 2008.
  • Noe, Reinhold; Hoffmann, Sebastian; Pfau, Timo; Adamczyk, Olaf; Herath, Vijitha; Peveling, Ralf; Porrmann, Mario:
    Realtime digital polarization and carrier recovery in a polarization-multiplexed optical QPSK transmission.
    In: Proceedings of the 2008 IEEE/LEOS Summer Topical Meetings, 2008. »»
    Abstract

    conference paper / id: 2494113

    Realtime digital polarization and carrier recovery in a polarization-multiplexed optical QPSK transmission

    Noe, Reinhold; Hoffmann, Sebastian; Pfau, Timo; Adamczyk, Olaf; Herath, Vijitha; Peveling, Ralf; Porrmann, Mario

    This paper presents a phase estimation algorithm for a synchronous optical QPSK transmission system. The algorithm has been used in a digital signal processing unit for realtime carrier and data recovery. It has further been combined with polarization multiplex and electronic polarization control.


    In: Proceedings of the 2008 IEEE/LEOS Summer Topical Meetings, 2008.
  • Witkowski, Ulf; El Habbal, Mohamed Ahmed Mostafa; Herbrechtsmeier, Stefan; Tanoto, Andry; Penders, Jacques; Alboul, Lyuba; Gazi, Veysel:
    Ad-hoc Network Communication Infrastructure for Multi-robot Systems in Disaster Scenarios.
    In: Proceedings of IARP/EURON Workshop on Robotics for Risky Interventions and Environmental Surveillance (RISE 2008), Benicassim, Spain, 2008. »»

    Ad-hoc Network Communication Infrastructure for Multi-robot Systems in Disaster Scenarios

    Witkowski, Ulf; El Habbal, Mohamed Ahmed Mostafa; Herbrechtsmeier, Stefan; Tanoto, Andry; Penders, Jacques; Alboul, Lyuba; Gazi, Veysel

    Mobile ad-hoc networks (MANETs) are communication networks that do not rely on fixed, preinstalled communication devices like base stations or predefined communication cells. MANETs are wireless networks consisting of mobile nodes which are characterized by their decentralized organization and the potentially high dynamics of the network structure. Therefore, MANETs are ideally suitable for applications with multi-robot systems. One of the most promising applications of a multi-robot system is to assist humans in urban search and rescue (USAR) scenarios in the aftermath of natural or man-made disasters. We are focusing on an ad-hoc network communication system with the mobile robots being communication nodes offering a robust communication infrastructure. Main disaster scenario covered by our system is a large industrial warehouse in fire, described in the GUARDIANS project funded by the European Union. In this scenario, black smoke may fill large space of the warehouse that makes it very difficult for the firefighters to orientate themselves in the building which in turn will usually limit the action space of the firefighters. In order to increase the coverage area of the fire fighters the ad-hoc network has to provide position data to support localization of the mobile robots and humans, which might be of great importance to guide the humans and robots to specific targets and locations or to quickly exit the search area. In our proposed approach a cell-based network with master nodes in each cell forms the basic structure of the network. Some nodes formed by speciallyequipped robots act as beacons to uniformly span the network. These robots have a role as reference points when positioning other mobile robots or humans and at the same time form the infrastructure to support communication all over the search area. A combination of distance and radio signal quality measurements as well as dedicated swarming behaviors of the robots are capable of maintaining suitable distribution of the robots even in the presence of walls that obstruct the radio signals. Communications standards considered for the ad-hoc network are Wireless LAN, Bluetooth and QigBee. All are integrated on a miniature robot for real experiments. The features of the network are studied analytically, in simulations as well as in experiments to verify the results. Furthermore, frequency and power managements are also taken into consideration to ensure robustness of communication in the network.


    In: Proceedings of IARP/EURON Workshop on Robotics for Risky Interventions and Environmental Surveillance (RISE 2008), Benicassim, Spain, 2008.
  • Ebied, Hala; Witkowski, Ulf; Rückert, Ulrich:
    Robot Localization Based on Visual Landmarks.
    In: The 5th IEEE International Conference on Informatics in Control, Automation and Robotics (ICINCO), 11-15 May-2008, Funchal, Madeira – Portugal., 2008. »»

    conference paper / id: 2289183

  • El Habbal, Mohamed Ahmed Mostafa; Witkowski, Ulf; Rückert, Ulrich:
    Mobile Ad-hoc Communication applied and optimized for disaster scenarios.
    In: Wireless Technologies Kongress 2008, 2008. »»

    conference paper / id: 2289215

  • Witkowski, Ulf; Wilhelm, Per; Parketny, Tobias:
    Einsatz von Low-Power Netzwerken zum Monitoring leistungsdiagnostischer Daten im Teamsport.
    In: Wireless Technologies Kongress 2008, 2008. »»
    Fulltext (PDF) Fulltext (external)

    conference paper / id: 2293502

  • Paiz, Carlos; Pohl, Christopher; Porrmann, Mario; Andrade-Cetto, Juan; Ferrier, Jean-Luis; dias Pereira, Jos'e Miguel Costa; Filipe, Joaquim:
    Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design..
    In: Informatics in Control, Automation and Robotics, Volume: 3, Springer-Verlag, 2008. »»
    Abstract

    book chapter / id: 2493607

    Hardware-in-the-Loop Simulations for FPGA-Based Digital Control Design.

    Paiz, Carlos; Pohl, Christopher; Porrmann, Mario

    A framework to perform hardware-in-the-loop (HIL) simulations in the designflow of digital controllers, based on Field Programmable Gate Array (FPGA) technology, is presented. The framework allows the interaction of digital controllers, implemented on our rapid prototyping system RAPTOR2000 with a Matlab/Simulink simulation running on a host computer. The underlying hardware and software designs supporting the interaction of the digital control and the simulation are presented. The designflow of FPGA-based digital controllers when using HIL is described and examples are given. Results from HIL simulations are presented, showing that the acceleration of the simulation increases with the complexity of the design when the number of I/Os stays constant. Furthermore, using the proposed HIL framework the clock accurate verification of the design can be achieved within the design phase.


    In: Informatics in Control, Automation and Robotics, Volume: 3, Springer-Verlag, 2008.
  • Pfau, Timo; Wördehoff, Christian; Peveling, Ralf; Ibrahim, Selwan K.; Hoffmann, Sebastian; Adamczyk, Olaf; Bhandare, Suhas; Porrmann, Mario; Noe, Reinhold; Porte, H.; Achiam, Y.; Hauden, Y.; Grossard, N.; Schlieder, D.; Koslovsky, A.:
    Ultra-Fast Adaptive Digital Polarization Control in a Realtime Coherent Polarization-Multiplexed QPSK Receiver.
    In: Proceedings of OFC/NFOEC 2008, 2008. »»
    Fulltext (external) Abstract

    conference paper / id: 2493900

    Ultra-Fast Adaptive Digital Polarization Control in a Realtime Coherent Polarization-Multiplexed QPSK Receiver

    Pfau, Timo; Wördehoff, Christian; Peveling, Ralf; Ibrahim, Selwan K.; Hoffmann, Sebastian; Adamczyk, Olaf; Bhandare, Suhas; Porrmann, Mario; Noe, Reinhold; Porte, H.; Achiam, Y.; Hauden, Y.; Grossard, N.; Schlieder, D.; Koslovsky, A.

    A digital polarization control system integrated in a 2.8 Gbit/s realtime polarization-multiplexed coherent QPSK system compensates for endless polarization changes having a maximum gradient of 3.5 krad/s (12 krad/s) with 1 dB (3.9 dB) loss in receiver sensitivity.


    In: Proceedings of OFC/NFOEC 2008, 2008.
  • Purnaprajna, M.; Puttmann, C.; Porrmann, Mario:
    Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography.
    In: Proceedings of DATE '08: Design, Automation and Test in Europe, DATE '08, 2008. »»
    Fulltext (external) Abstract

    conference paper / id: 2493929

    Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography

    Purnaprajna, M.; Puttmann, C.; Porrmann, Mario

    Reconfigurable architectures are being increasingly used for their flexibility and extensive parallelism to achieve accelerations for computationally intensive applications. Although these architectures provide easy adaptability, it is so with an overhead in terms of area, power and timing, as compared to non-reconfigurable ASICs. Here, we propose a low overhead reconfigurable multiprocessor, which provides both parallelism and flexibility. The architecture has been evaluated for its energy efficiency for a computational intensive algorithm used in elliptic curve cryptography (ECC). Typically, algorithms in ECC exhibit task-level parallelism and demand large amount of computational resources for custom implementations to achieve a significant speedup. A finite field multiplication in GF(2^233) was chosen as a sample application to evaluate the performance on the QuadroCore reconfigurable multiprocessor architecture. A three-fold performance improvement as compared to a single processor implementation was observed. Further, via reconfiguration to suit the application, power savings of about 24% were noted in UMC's 90nm standard cell technology.


    In: Proceedings of DATE '08: Design, Automation and Test in Europe, DATE '08, 2008.
  • Pohl, Christopher; Paiz, Carlos; Porrmann, Mario:
    A Hardware-in-the-Loop Design Environment for FPGAs.
    In: Design, Automation and Test in Europe (DATE), University Booth, 2008. »»

    conference paper / id: 2494491

2007
  • Köster, M.; Kalte, H.; Porrmann, Mario; Rückert, Ulrich:
    Defragmentation Algorithms for Partially Reconfigurable Hardware.
    In: VLSI-SoC: From Systems to Silicon, Volume: 240, Springer, 2007. »»
    Abstract

    article / id: 2285724

    Defragmentation Algorithms for Partially Reconfigurable Hardware

    Köster, M.; Kalte, H.; Porrmann, Mario; Rückert, Ulrich

    Dynamic reconfiguration is a promising approach for resource efficient utilization of microelectronic systems. Standard platforms for partial dynamic reconfiguration are field-programmable gate arrays (FPGAs). Multiple hardware tasks can share the same FPGA resources over time, which increases the device utilization in comparison to non-reconfigurable systems. Although, similar resource management is already known in the area of operating systems, there is a requirement to adapt these concepts to the special needs of dynamically reconfigurable systems. Additionally, there is a lack of underlying mechanisms, e.g., to suspend hardware tasks and restart them at a different position within the FPGA. In this article we introduce a mechanism for task relocation that includes saving and restoring of state information of the task. Based on this approach we address the problem of defragmentation. We present defragmentation algorithms that minimize different types of costs. With the help of a detailed simulation model and a benchmark, we finally provide realistic simulation results and compare the different algorithms.


    In: VLSI-SoC: From Systems to Silicon, Volume: 240, Springer, 2007.
  • Xu, Feng; Rückert, Ulrich:
    SSB: A new diversity selection combining scheme and its test-bed implementation.
    In: Telecommunications and Malaysia International Conference on Communications, 2007. ICT-MICC 2007. IEEE International Conference on, 2007. »»
    Abstract

    conference paper / id: 2286265

    SSB: A new diversity selection combining scheme and its test-bed implementation

    Xu, Feng; Rückert, Ulrich

    SSB (Simplified Switched Beam) was originallymotivated by a simple beamforming technique. It is expected toincrease the performance of Mobile Ad Hoc Networks (MANETs)by associating with the dedicated MAC protocol [12]. However,we further find that it is a variation of the antenna diversityscheme, which is called GSC in [6] and H-S/MRC in [11]. SSBonly requires one RF front-end and a simple additional processingunit, hence it has apparent advantage in terms of size, power,expense and complexity. Its 2.4 GHz test-bed for reception hasbeen implemented recently. Intensive measurements show thatSSB can help to suppress the effect of fading, enhance the SNRand finally result in the reduced BER.


    In: Telecommunications and Malaysia International Conference on Communications, 2007. ICT-MICC 2007. IEEE International Conference on, 2007.
  • Du, Jia Lei; Tanoto, Andry; Monier, Emad; Witkowski, Ulf; Rückert, Ulrich:
    Multi-Robotics Experiments using Mini-Robots.
    In: Proceedings of the 3rd International Conference on Intelligent Computing and Information Systems (ICICIS 2007), 2007. »»

    conference paper / id: 2289149

  • Pfau, Timo; Peveling, Ralf; Hauden, Y.; Grossard, N.; Porte, H.; Achiam, Y.; Hoffmann, Sebastian; Ibrahim, Selwan K.; Adamczyk, Olaf; Bhandare, Suhas; Sandel, D; Porrmann, Mario; Noe, Reinhold:
    Coherent Digital Polarization Diversity Receiver for Real-Time Polarization-Multiplexed QPSK Transmission at 2.8 Gb/s.
    In: Photonics Technology Letters, IEEE, Volume: 19, 2007. »»
    Abstract

    article / id: 2493699

    Coherent Digital Polarization Diversity Receiver for Real-Time Polarization-Multiplexed QPSK Transmission at 2.8 Gb/s

    Pfau, Timo; Peveling, Ralf; Hauden, Y.; Grossard, N.; Porte, H.; Achiam, Y.; Hoffmann, Sebastian; Ibrahim, Selwan K.; Adamczyk, Olaf; Bhandare, Suhas; Sandel, D; Porrmann, Mario; Noe, Reinhold

    This letter presents a coherent digital polarization diversity receiver for real-time polarization-multiplexed synchronous quadrature phase-shift keying transmission with distributed feedback lasers at a data rate of 2.8 Gb/s. The tolerance against fast polarization changes and polarization-dependent loss is evaluated for different filter widths in the carrier recovery circuit. The minimum achieved bit-error rate is 3.4 times 10-7.


    In: Photonics Technology Letters, IEEE, Volume: 19, 2007.
  • Pohl, Christopher; Paiz, Carlos; Porrmann, Mario:
    Hardware-in-the-Loop Entwicklungsumgebung fuer informationsverarbeitende Komponenten mechatronischer Systeme.
    In: 5. Paderborner Workshop Entwurf mechatronischer Systeme, 2007. »»

    conference paper / id: 2494159

  • Pfau, Timo; Adamczyk, Olaf; Herath, Vijitha; Peveling, Ralf; Hoffmann, Sebastian; Porrmann, Mario; Noe, Reinhold:
    Realtime Optical Synchronous QPSK Transmission with DFB lasers.
    In: Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, 2007. »»
    Abstract

    conference paper / id: 2494262

    Realtime Optical Synchronous QPSK Transmission with DFB lasers

    Pfau, Timo; Adamczyk, Olaf; Herath, Vijitha; Peveling, Ralf; Hoffmann, Sebastian; Porrmann, Mario; Noe, Reinhold

    This paper focuses on the design of the components required to realize a 10 Gbaud synchronous optical quadrature phase shift keying (QPSK) transmission system. These are a 5 bit 10 Gsamples/s analog-to-digital converter and a digital signal processing unit for carrier and data recovery.


    In: Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, 2007.
  • Niemann, Jörg-Christian; Puttmann, Christoph; Porrmann, Mario; Rückert, Ulrich:
    Resource efficiency of the GigaNetIC chip multiprocessor architecture.
    In: Journal of System Architecture, Volume: 53, 2007. »»
    Abstract

    article / id: 2145016

    Resource efficiency of the GigaNetIC chip multiprocessor architecture

    Niemann, Jörg-Christian; Puttmann, Christoph; Porrmann, Mario; Rückert, Ulrich

    In this article, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before fabricating the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with various performance and throughput requirements at high reliability. Furthermore, the composition based on predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators. Finally, we compare implementations of our architecture with state-of-the-art desktop CPUs. We use simple, general-purpose applications as well as the introduced packet processing tasks to determine the performance capabilities and the resource efficiency of the GigaNetIC architecture. We show that, if supported by the application, parallelism offers more opportunities than increasing clock frequencies.


    In: Journal of System Architecture, Volume: 53, 2007.
  • Xu, Feng; Rückert, Ulrich:
    Interference Suppression Technique for Diversity Selection Combining in an Indoor Environment.
    In: Antennas, 2007. INICA '07. 2nd International ITG Conference on, 2007. »»
    Abstract

    conference paper / id: 2286187

    Interference Suppression Technique for Diversity Selection Combining in an Indoor Environment

    Xu, Feng; Rückert, Ulrich

    In this paper a new diversity selection combiningscheme called SSB (simplified switched beam) is given, as wellas its test-bed implementation. SSB has apparent advantage interms of size, power and complexity since it only requires oneRF front-end and very few additional components. Furthermore,an interference suppression technique is designed, which caneffectively mitigate the disturbance on correct diversity selectioncaused by interference. The intensive measurements made in anindoor environment show that this test-bed can closely approachthe theoretical prediction on SNR gain and AF (amount of fading)made in [4] and [9] previously.


    In: Antennas, 2007. INICA '07. 2nd International ITG Conference on, 2007.
  • Paiz, Carlos; Kettelhoit, Boris; Porrmann, Mario:
    A design framework for FPGA-based dynamically reconfigurable digital controllers.
    In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS2007), 2007. »»
    Abstract

    conference paper / id: 2494165

    A design framework for FPGA-based dynamically reconfigurable digital controllers

    Paiz, Carlos; Kettelhoit, Boris; Porrmann, Mario

    During the past years, it has been shown that dynamic reconfiguration of FPGAs can be used to enhance the resource efficiency and flexibility of digital controllers. The authors have developed a system architecture, which allows the reconfiguration of FPGA-implemented controllers during runtime. Depending on the operating regions of the controlled plant different controllers can be dynamically loaded into the system. In this paper we present a design flow that enables an automated generation of such partial controllers. Furthermore, a high-level design entry allows a comfortable simulation of the controllers with sophisticated tools such as Matlab Simulink.


    In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS2007), 2007.
  • Pfau, Timo; Peveling, Ralf; Hoffmann, Sebastian; Bhandare, Suhas; Ibrahim, Selwan K.; Sandel, D; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold; Achiam, Y.; Schlieder, D.; Koslovsky, A.; Benarush, Y.; Hauden, Y.; Grossard, N.; Porte, H.:
    PDL-Tolerant Real-time Polarization-Multiplexed QPSK Transmission with Digital Coherent Polarization Diversity Receiver.
    In: Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, 2007. »»
    Abstract

    conference paper / id: 2494230

    PDL-Tolerant Real-time Polarization-Multiplexed QPSK Transmission with Digital Coherent Polarization Diversity Receiver

    Pfau, Timo; Peveling, Ralf; Hoffmann, Sebastian; Bhandare, Suhas; Ibrahim, Selwan K.; Sandel, D; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold; Achiam, Y.; Schlieder, D.; Koslovsky, A.; Benarush, Y.; Hauden, Y.; Grossard, N.; Porte, H.

    This paper presents the implementation of a real-time electronic polarization tracking algorithm which enables robust optical polarization-multiplexed synchronous quadrature phase shift keying transmission with DFB lasers. The achieved BER at a data rate of 2.8 Gbit/s is well below the FEC threshold.


    In: Proceedings of the 2007 IEEE/LEOS Summer Topical Meetings, 2007.
  • Pfau, Timo; Peveling, Ralf; Samson, Florian; Romoth, Johannes; Hoffmann, Sebastian; Bhandare, Suhas; Ibrahim, Selwan K.; Sandel, D; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold; Hauden, Y.; Grossard, N.; Porte, H.; Schlieder, D.; Koslovsky, A.; Benarush, Y.; Achiam, Y.:
    Polarization-Multiplexed 2.8 Gbit/s Synchronous QPSK Transmission with Real-Time Digital Polarization Tracking.
    In: Proceedings of ECOC, Volume: 3, 2007. »»
    Fulltext (external) Abstract

    conference paper / id: 2494285

    Polarization-Multiplexed 2.8 Gbit/s Synchronous QPSK Transmission with Real-Time Digital Polarization Tracking

    Pfau, Timo; Peveling, Ralf; Samson, Florian; Romoth, Johannes; Hoffmann, Sebastian; Bhandare, Suhas; Ibrahim, Selwan K.; Sandel, D; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold; Hauden, Y.; Grossard, N.; Porte, H.; Schlieder, D.; Koslovsky, A.; Benarush, Y.; Achiam, Y.

    This paper presents the implementation of an electronic polarization tracking algorithm which enables real-time polarization-multiplexed synchronous QPSK transmission with DFB lasers. The achieved BER at 2.8 Gbit/s is well below the FEC threshold.


    In: Proceedings of ECOC, Volume: 3, 2007.
  • Porrmann, Mario:
    Flexible Hardware Platforms for Dynamic Reconfiguration.
    In: Invited Talk at the 2nd Int. Conf. on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop, 2007. »»

    conference paper / id: 2494514

  • Schulz, Bernd; Paiz, Carlos; Hagemeyer, Jens; Mathapati, Shashidhar; Porrmann, Mario; Böcker, Joachim:
    Run-Time Reconfiguration of FPGA-Based Drive Controllers.
    In: European Conference on Power Electronics and Applications (EPE 2007), 2007. »»
    Abstract

    conference paper / id: 2472729

    Run-Time Reconfiguration of FPGA-Based Drive Controllers

    Schulz, Bernd; Paiz, Carlos; Hagemeyer, Jens; Mathapati, Shashidhar; Porrmann, Mario; Böcker, Joachim

    In this contribution a field programmable gate array (FPGA) is used as target architecture to implement drive controllers. A novel concept for generic run-time switching between FPGA-based drive controllers is presented. The controller switching is done by using partial run-time hardware reconfiguration, which allows the implementation of various controllers without having to realize them all on the FPGA concurrently. It is shown that time-sharing of the FPGA resources can provide a resource-efficient implementation. A system architecture, which enables the realization of this scheme, is presented. A hard switching between controllers is implemented, for which the initial internal states of the controller to-be-loaded are computed. Experimental results show that the proposed scheme works satisfactory, opening new possibilities to the implementation of such adaptive control schemes.


    In: European Conference on Power Electronics and Applications (EPE 2007), 2007.
  • Hagemeyer, Jens; Kettelhoit, Boris; Koester, Markus; Porrmann, Mario:
    A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS.
    In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007. »»
    Abstract

    conference paper / id: 2472743

    A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS

    Hagemeyer, Jens; Kettelhoit, Boris; Koester, Markus; Porrmann, Mario

    The ability of partial reconfiguration of today's FPGAs allows the exchange of dynamic system components at runtime, which enables the realization of self-reconfigurable systems. To ease the design of a partially reconfigurable system this paper presents an integrated design flow for reconfigurable architectures. The design flow includes tools for system partitioning, floorplanning, and automatic generation of configuration data for the static and the dynamic system components. Furthermore, the design flow comprises the implementation of a homogeneous on-chip communication infrastructure, which is used to interconnect the dynamic system components placed at run-time. For the design of such an on-chip communication infrastructure a layer model is introduced, which divides the communication into five different layers of abstraction. As an example a communication infrastructure is realized on a Xilinx Virtex-2 FPGA based on the Wishbone protocol. A tristate-based and a slice-based implementation are presented and analyzed with respect to efficiency.


    In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.
  • Hagemeyer, Jens; Kettelhoit, Boris; Koester, Markus; Porrmann, Mario:
    INDRA – Integrated Design Flow for Reconfigurable Architectures.
    In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth, 2007. »»
    Fulltext (external) Abstract

    conference paper / id: 2472748

    INDRA – Integrated Design Flow for Reconfigurable Architectures

    Hagemeyer, Jens; Kettelhoit, Boris; Koester, Markus; Porrmann, Mario

    INDRA offers a solution for an automated design flow of heterogeneous partially reconfigurable systems utilizing advanced features such as a flexible placement and com-munication for hardware modules.


    In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth, 2007.
  • Rana, V.; Santambrogio, M.; Sciuto, D.; Kettelhoit, B.; Koester, M.; Porrmann, Mario; Rückert, Ulrich:
    Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.
    In: Proceedings of the 21st International Parallel and Distributed Processing Symposium (IPDPS 2007) - Reconfigurable Architecture Workshop (RAW), IEEE Computer Society., 2007. »»
    Abstract

    conference paper / id: 2285993

    Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux

    Rana, V.; Santambrogio, M.; Sciuto, D.; Kettelhoit, B.; Koester, M.; Porrmann, Mario; Rückert, Ulrich

    Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a Multi-FPGA Clustered Architecture (MFCA). All FPGAs can be partially and dynamically reconfigured to integrate user-defined IPCores into the system at run-time. For the resource management and communication management we have implemented a Linux Operating System on the embedded processor that can be used to control the reconfiguration of the FPGAs by means of simple function calls. Furthermore, the Linux OS completely hides the physical infrastructure of the MFCA from user applications, offering a consistent interface to utilize partial reconfiguration.


    In: Proceedings of the 21st International Parallel and Distributed Processing Symposium (IPDPS 2007) - Reconfigurable Architecture Workshop (RAW), IEEE Computer Society., 2007.
  • Kaulmann, Tim; Lütkemeier, Sven; Rückert, Ulrich:
    IAF Neuron Implementation for Mixed-Signal PCNN Hardware.
    In: Proceedings of the 9th International Work-Conference on Artificial Neural Networks (IWANN), Springer-Verlag, 2007. »»
    Abstract

    conference paper / id: 2289096

    IAF Neuron Implementation for Mixed-Signal PCNN Hardware

    Kaulmann, Tim; Lütkemeier, Sven; Rückert, Ulrich

    In this paper, the implementation results of an integrate and fire neuron implemented in a 130 nm process are presented. This publication covers the properties of IAF neurons from calculations on an ideal electrical circuit modeling the soma of an IAF neuron and compares the theoretical results with simulation results from an extracted layout of the implemented neuron.


    In: Proceedings of the 9th International Work-Conference on Artificial Neural Networks (IWANN), Springer-Verlag, 2007.
  • Wilhelm, Per:
    Hardware im Trikot – Dank moderner IT zu sportlichen Höchstleistungen.
    In: 50 Entwürfe junger Wissenschaftler für die Welt von morgen, Heel Verlag, 2007. »»

    book chapter / id: 2293516

  • Kaulmann, T.; Dikmen, D.; Rückert, Ulrich:
    A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation.
    In: Hybrid Intelligent Systems, 2007. HIS 2007. 7th International Conference on, 2007. »»
    Fulltext (external) Abstract

    conference paper / id: 2286250

    A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation

    Kaulmann, T.; Dikmen, D.; Rückert, Ulrich

    This publication presents a digital framework for build- ing up pulse coded neural networks with leaky integrate- and-fire neurons and static synapses as well as dynamic synapses. The system, including a novel communication in- frastructure, is mainly focused on ASIC synthesis but also shows a small footprint on Virtex2(Pro) FPGAs. Its bit- serial operation has been verified by simulations.


    In: Hybrid Intelligent Systems, 2007. HIS 2007. 7th International Conference on, 2007.
  • Hussmann, Michael; Thies, Michael; Kastens, Uwe; Purnaprajna, Madhura; Porrmann, Mario; Rückert, Ulrich:
    Compiler-Driven Reconfiguration of Multiprocessors.
    In: Proceedings of the Workshop on Application Specific Processors (WASP) 2007, 2007. »»

    Compiler-Driven Reconfiguration of Multiprocessors

    Hussmann, Michael; Thies, Michael; Kastens, Uwe; Purnaprajna, Madhura; Porrmann, Mario; Rückert, Ulrich

    Multiprocessors enable parallel execution of a single large application to achieve a performance improvement. An application is split at instruction, data or task level (based on the granularity), such that the overhead of partitioning is minimal. Parallelization for multiprocessors is mostly restricted to a fixed granularity. Reconfiguration enables architectural variations to allow multiple granularities of operation within a multiprocessor. This adaptability optimizes resource utilization over a fixed organization. Here, a unified hardware-software approach to design a reconfigurable multiprocessor system called QuadroCore is presented. In our holistic methodology, compiler-driven reconfiguration selects from a fixed set of modes. Each mode relies on matching program analysis to exploit the architecture efficiently. For instance, a multiprocessor may adapt to different parallelization paradigms. The compiler can determine the best execution mode for each piece of code by analyzing the parallelism in a program. A fast, singlecycle, run-time reconfiguration between these predetermined modes is enabled by executing special instructions which switch coarse-grained components like instruction decoders, ALUs and register banks. Performance is evaluated in terms of execution cycles and achieved clock frequency. First results indicate suitability especially in audio and video processing applications.


    In: Proceedings of the Workshop on Application Specific Processors (WASP) 2007, 2007.
  • Jungeblut, Thorsten; Grünewald, Matthias; Porrmann, Mario; Rückert, Ulrich:
    Real-Time Multiprocessor SoC for Mobile Ad Hoc Networks.
    In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth, 2007, 2007. »»
    Fulltext (external) Abstract

    conference paper / id: 2289057

    Real-Time Multiprocessor SoC for Mobile Ad Hoc Networks

    Jungeblut, Thorsten; Grünewald, Matthias; Porrmann, Mario; Rückert, Ulrich

    This paper introduces our Real-time Multiprocessor SoC intended for low power wireless application as mobile ad hoc networks. The multiprocessor is based on eight of our 32bit S-CORE RISC processors.


    In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth, 2007, 2007.
  • Eickhoff, Ralf; Kaulmann, Tim; Rückert, Ulrich:
    Neural Inspired Architectures for Nanoelectronics.
    In: Proceedings of the 9th International Work-Conference on Artificial Neural Networks (IWANN), Springer-Verlag, 2007. »»
    Abstract

    conference paper / id: 2289076

    Neural Inspired Architectures for Nanoelectronics

    Eickhoff, Ralf; Kaulmann, Tim; Rückert, Ulrich

    Extremely down-scaled field effect transistor, innovativemanufacturing of semiconductors, novel material and computing devices have led to rapid changes in the semiconductor industry which now allows more complex systems and more computing power per chip area than several years ago. Albeit these significant improvements novel technology nodes also offer unsolved problems to researchers and challenges to the designers. In this paper, we give a brief overview about actual trends and problems in the semiconductor industry and how the upcoming tasks can be solved by the designers and researchers.


    In: Proceedings of the 9th International Work-Conference on Artificial Neural Networks (IWANN), Springer-Verlag, 2007.
  • Tanoto, Andry; Witkowski, Ulf; Rückert, Ulrich:
    Teleworkbench: A Remotely-Accessible Robotic Laboratory foe Education.
    In: Spring 2007 AAAI Symposium on Robots in AI and CS Education-Robots and Robot Venues: Resources for AI Education, 2007. »»

    Teleworkbench: A Remotely-Accessible Robotic Laboratory foe Education

    Tanoto, Andry; Witkowski, Ulf; Rückert, Ulrich

    This paper presents a teleoperated robotic-laboratory named Teleworkbench and its benefit for educational purpose. It also presents briefly three issues that we need to take into consideration to make such a laboratory more effective.


    In: Spring 2007 AAAI Symposium on Robots in AI and CS Education-Robots and Robot Venues: Resources for AI Education, 2007.
  • Kaulmann, Tim; Löffler, Axel; Rückert, Ulrich:
    A Control Approach to a Biophysical Neuron Model.
    In: Proceedings of the International Conference on Artificial Neural Networks, Springer-Verlag, 2007. »»
    Abstract

    conference paper / id: 2289108

    A Control Approach to a Biophysical Neuron Model

    Kaulmann, Tim; Löffler, Axel; Rückert, Ulrich

    In this paper we present a neuron model based on the description of biophysical mechanisms combined with a regulatory mechanism from control theory. The aim of this work is to provide a neuron model that is capable of describing the main features of biological neurons such as maintaining an equilibrium potential using the NaK-ATPase and the generation of action potentials as well as to provide an estimation of the energy consumption of a single cell in a) quiescent mode (or equilibrium state) and b) firing state, when excited by other neurons. The same mechanism has also been used to model the synaptic excitation used in the simulated system.


    In: Proceedings of the International Conference on Artificial Neural Networks, Springer-Verlag, 2007.
  • El Habbal, Mohamed Ahmed Mostafa; Witkowski, Ulf; Rückert, Ulrich:
    FPGA based speech processing for the Khepera Robot.
    In: 4th International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), 2007. »»

    conference paper / id: 2289127

  • Amin, Safaa; Tanoto, Andry; Witkowski, Ulf; Rückert, Ulrich; Abdel-Wahaab, Mohammad:
    Environment Exploration Using Mini-Robot Khepera.
    In: International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE 2007), 2007. »»

    conference paper / id: 2289139

  • Rückert, Ulrich; Eickhoff, Ralf:
    Controlling complexity of RBF networks by similarity.
    In: ESANN, 2007. »»

    Controlling complexity of RBF networks by similarity

    Rückert, Ulrich; Eickhoff, Ralf

    Using radial basis function networks for function approximation tasks suffers from unavailable knowledge about an adequate network size. In this work, a measuring technique is proposed which can control the model complexity and is based on the correlation coefficient between two basis functions. Simulation results show good performance and, therefore, this technique can be integrated in the RBF training procedure.


    In: ESANN, 2007.
  • Noe, Reinhold; Pfau, Timo; Adamczyk, Olaf; Peveling, Ralf; Herath, Vijitha; Hoffmann, Sebastian; Porrmann, Mario; Ibrahim, Selwan K.; Bhandare, Suhas:
    Real-time Digital Carrier & Data Recovery for a Synchronous Optical Quadrature Phase Shift Keying Transmission System.
    In: Proceedings of System Microwave Symposium. IEEE/MTT-S International, 2007. »»
    Abstract

    conference paper / id: 2494202

    Real-time Digital Carrier & Data Recovery for a Synchronous Optical Quadrature Phase Shift Keying Transmission System

    Noe, Reinhold; Pfau, Timo; Adamczyk, Olaf; Peveling, Ralf; Herath, Vijitha; Hoffmann, Sebastian; Porrmann, Mario; Ibrahim, Selwan K.; Bhandare, Suhas

    This paper focuses on the recent progress in coherent optical communication using advanced digital signal processing (DSP) technology. In particular the design of DSP components is presented which are required to realize a 10 Gbaud synchronous optical quadrature phase shift keying (QPSK) transmission system. Additionally the measurement results of a preliminary synchronous QPSK transmission setup with distributed feedback (DFB) lasers and real-time digital in-phase and quadrature (I&Q) receiver at a data rate of 1.4 Gbit/s are shown. The minimum bit error ratio (BER) was 1.7ldr10-5, lower than ever reported before for a real-time system with DFB lasers.


    In: Proceedings of System Microwave Symposium. IEEE/MTT-S International, 2007.
  • Porrmann, Mario:
    A Layer-Model Based Methodology for the Design of Dynamically Reconfigurable Systems.
    In: Invited Talk at the 2nd Int. Conf. on Industrial and Information Systems (ICIIS 2007), Reconfigurable Computing Workshop, 2007. »»

    conference paper / id: 2494512

  • Sitte, Joaquin; Zhang, Liang; Rückert, Ulrich:
    Characterization of Analog Local Cluster Neural Network Hardware for Control.
    In: IEEE Transactions on Neural Networks, Special Issue on Neural Networks for Feedback Control Systems, Volume: 18, 2007. »»
    Abstract

    article / id: 2145075

    Characterization of Analog Local Cluster Neural Network Hardware for Control

    Sitte, Joaquin; Zhang, Liang; Rückert, Ulrich

    The local cluster neural network (LCNN) was designed for analog realization especially suited to applications in control systems. It uses clusters of sigmoidal neurons to generate basis functions that are localized in multidimensional input space. Sigmoidal neurons are well suited to analog electronic realization. In this paper, we report the results of extensive measurements that characterize the computational capabilities of the first analog very large scale integration (VLSI) realization of the LCNN. Despite manufacturing fluctuations and the inherent low precision of analog electronics, the test results suggest that it may be suitable for use in feedback control systems.


    In: IEEE Transactions on Neural Networks, Special Issue on Neural Networks for Feedback Control Systems, Volume: 18, 2007.
  • Eickhoff, Ralf; Rückert, Ulrich:
    Robustness of radial basis functions.
    In: Neurocomputing, Volume: 70, 2007. »»
    Fulltext (external) Abstract

    article / id: 2145265

    Robustness of radial basis functions

    Eickhoff, Ralf; Rückert, Ulrich

    Neural networks are intended to be used in future nanoelectronic technology since these architectures seem to be robust to malfunctioning elements and noise in its inputs and parameters. In this work, the robustness of radial basis function networks is analyzed in order to operate in noisy and unreliable environment. Furthermore, upper bounds on the mean square error under noise contaminated parameters and inputs are determined if the network parameters are constrained. To achieve robuster neural network architectures fundamental methods are introduced to identify sensitive parameters and neurons.


    In: Neurocomputing, Volume: 70, 2007.
  • Rückert, Ulrich; Sitte, Joaquin; Witkowski, Ulf:
    Autonomous Minirobots for Research and Edutainment.
    In: Volume: 216, Heinz Nixdorf Institut, Universität Paderborn, 2007. »»
    Abstract

    conference publication / id: 2285612

    Autonomous Minirobots for Research and Edutainment

    This paper describes the motivation, system architecture and design details of a mini robot for research and education. The main objective is to produce a set of electronic modules for sensor processing, actuator control and cognitive processing that fully utilise currently available electronics technology for the construction of mini robots capable of rich autonomous behaviours. These modules are used for the two wheeled AMiRo mini robot that meets the size requirements for participation in the AMiRESoT robot soccer league. All mechanical parts for the robot are off-the-shelf components or can be fabricated with common drilling, turning and milling machines. The connection between the modules is well defined and supports standard interfaces from parallel camera capture interfaces down to simple serial interfaces.


    In: Volume: 216, Heinz Nixdorf Institut, Universität Paderborn, 2007.
  • Rückert, Ulrich:
    Abschlußbericht zum BMBF-Projekt: NGN-PlaNets: Platforms for Networked Services.
    In: Heinz Nixdorf Institut, Universität Paderborn, 2007. »»

    report / id: 2285787

  • Puttmann, C.; Niemann, J.-C.; Porrmann, Mario; Rückert, Ulrich:
    GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors.
    In: Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on, 2007. »»
    Fulltext (external) Abstract

    conference paper / id: 2286362

    GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors

    Puttmann, C.; Niemann, J.-C.; Porrmann, Mario; Rückert, Ulrich

    Due to the technological progress in the semiconductor industry, more and more components can be integrated on a single die forming a complex System-on-Chip. For enabling an efficient interaction between the various building blocks of today’s SoCs, efficient communication structures become more and more essential. In this paper, we present the GigaNoC, a hierarchical Network-on-Chip that is especially suitable for scalable Chip-Multiprocessor architectures. The GigaNoC approach features a packet-switched wormhole routing on-chip network that provides the backbone of our multiprocessor architecture. In order to meet bandwidth requirements of different application domains, our Network-on-Chip is easily scalable and parameterizable in various aspects. This work highlights the communication protocol and shows a performance evaluation for different congestion scenarios. Furthermore, we present an FPGA-based prototypical realization and introduce a debugging and verification environment. Finally, implementation results for a standard cell technology are discussed.


    In: Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on, 2007.
  • Niemann, Jörg-Christian; Liß, Christian; Porrmann, Mario; Rückert, Ulrich:
    A Multiprocessor Cache for Massively Parallel SoC Architectures.
    In: ARCS'07: Architecture of Computing Systems, 2007. »»
    Abstract

    conference paper / id: 2289049

    A Multiprocessor Cache for Massively Parallel SoC Architectures

    Niemann, Jörg-Christian; Liß, Christian; Porrmann, Mario; Rückert, Ulrich

    In this paper, we present an advanced multiprocessor cache architecture for chip multiprocessors (CMPs). It is designed for the scalable GigaNetIC CMP, which is based on massively parallel on-chip computing clusters. Our write-through multiprocessor cache is configurable in respect to the most relevant design options. It is supposed to be used in universal co-processors as well as in network processing units. For an early verification of the software and an early exploration of various hardware configurations, we have developed a SystemC-based simulation model for the complete chip multiprocessor. For detailed hardware-software co-verification, we use our FPGA-based rapid prototyping system RAPTOR2000 to emulate our architecture with near-ASIC performance. Finally, we demonstrate the performance gains for different application scenarios enabled by the usage of our multiprocessor cache.


    In: ARCS'07: Architecture of Computing Systems, 2007.
  • Eickhoff, Ralf; Kaulmann, Tim; Rückert, Ulrich:
    Impact of shrinking technologies on the activation function of neurons.
    In: Proceedings of the International Conference on Artificial Neural Networks, Springer-Verlag, 2007. »»
    Abstract

    conference paper / id: 2289102

    Impact of shrinking technologies on the activation function of neurons

    Eickhoff, Ralf; Kaulmann, Tim; Rückert, Ulrich

    Artificial neural networks are able to solve a great variety of different applications, e.g. classification or approximation tasks. To utilize their advantages in technical systems various hardware realizations do exist. In this work, the impact of shrinking device sizes on the activation function of neurons is investigated with respect to area demands, power consumption and the maximum resolution in their information processing. Furthermore, analog and digital implementations are compared in emerging silicon technologies beyond 100 nm feature size.


    In: Proceedings of the International Conference on Artificial Neural Networks, Springer-Verlag, 2007.
  • Du, Jia Lei; Witkowski, Ulf; Rückert, Ulrich:
    A Bluetooth Scatternet for the Khepera Robot.
    In: 4th International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), 2007. »»

    A Bluetooth Scatternet for the Khepera Robot

    Du, Jia Lei; Witkowski, Ulf; Rückert, Ulrich

    Radio-based communication plays a vital role in multi-robot systems. Bluetooth is an energy-efficient communication technology suited for resourcelimited mini-robots such as the Khepera. However, the maximum number of nodes in a Bluetooth piconet is limited, while scatternets - networks of piconets - have not been fully specified. In this paper we present a Bluetooth scatternet using Bluetooth communication sticks developed in our research group. In our solution, bridge nodes carrying two of such Bluetooth sticks are used to interconnect piconets. Beside the developed hardware, issues such as routing as well as topology control are addressed. Finally, data rate and latency measurements are presented for the implemented solution.


    In: 4th International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), 2007.
  • Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich:
    Stereoscopic Camera for Autonomous Mini-Robots Applied in KheperaSot League.
    In: FIRA Robot World Congress 2007, on CD, 2007. »»

    Stereoscopic Camera for Autonomous Mini-Robots Applied in KheperaSot League

    Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich

    This paper presents a stereoscopic vision system for the mini-robot Khepera. The vision system performs objects detection by using the stereo disparity and stereo correspondence. The stereoscopic vision system enhances robot’s visual perception ability by grabbing stereo images and analysis 3D objects, while the robot doesn’t need to move. The simple principle of our stereo vision is the less displacement of correspondence pixels shows that the pixels object is far away. To realize the stereo vision and its calculation algorithms, the mini robot needs a powerful FPGA and micro-controller module as well as 2D color cameras. An application of Khepera equipped with the stereoscopic camera is robot soccer in the KheperaSot league. In the match, the robot has to be able to detect its environment, i.e. the ball, walls, goals and its opponent.


    In: FIRA Robot World Congress 2007, on CD, 2007.
  • Ebied, Hala; Witkowski, Ulf; Rückert, Ulrich:
    Robot Localization System Based on 2D-Color Vision Sensor.
    In: The 4th International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), 2-5 October 2007, Buenos Aires, Argentina., 2007. »»

    conference paper / id: 2289133

  • Paiz, Carlos; Porrmann, Mario:
    The Utilization of Reconfigurable Hardware to Implement Digital Controllers: a Review.
    In: Proceedings of the IEEE International Symposium on Industrial Electronics, 2007. »»
    Abstract

    conference paper / id: 2494198

    The Utilization of Reconfigurable Hardware to Implement Digital Controllers: a Review

    Paiz, Carlos; Porrmann, Mario

    This paper reviews the impact of Reconfigurable Hardware (RH) on the design of digital controllers. It starts by showing the application areas in which this technology has more influence. The reasons of the technology migration are then analyzed, pointing specific examples from the literature. Finally, run-time reconfiguration (RTR) of Field Programmable Gate Arrays (FPGAs) is revised and its utilization for designing FPGA-based controllers is presented. The research trends are shown, giving an insight on the potential benefits of using this technology.


    In: Proceedings of the IEEE International Symposium on Industrial Electronics, 2007.
  • Hagemeyer, Jens; Kettelhoit, Boris; Koester, Markus; Porrmann, Mario:
    Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs.
    In: Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07), 2007. »»
    Fulltext (external) Abstract

    conference paper / id: 2472738

    Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs

    Hagemeyer, Jens; Kettelhoit, Boris; Koester, Markus; Porrmann, Mario

    Dynamic reconfiguration is a promising approach to enhance the resource efficiency of FPGAs beyond the current possibilities. One of the main prerequisites for its implementation is a communication infrastructure that enables data transfer between the hardware modules that are placed on the FPGA at run-time. In this paper we present a new communication macro for Xilinx FPGAs that considers the special requirements of these systems. While most solutions that were presented so far enable basic communication between a low number of hardware modules at fixed positions, our approach implements an infrastructure that allows free placement of hardware modules at run-time. Methodologies like 2D-placement of modules, which were analyzed mainly in theory so far, can now be implemented with currently available FPGAs. A tool-flow is presented, that automatically generates the required homogeneous communication infrastructure for any FPGA of the Xilinx Virtex-E to Virtex-5 family. Performance and area requirements are analyzed based on two typical example implementations of a Wishbone bus. 1.


    In: Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07), 2007.
2006
  • Witkowski, Ulf; Chinapirom, Teerapat; Rückert, Ulrich:
    Self-Orientation of Soccer Robots on Soccer Pitch by Identifying Pitch Lines.
    In: Proceedings of FIRA RoboWorld Congress, 2006. »»

    conference paper / id: 2288994

  • Kaulmann, Tim; Witkowski, Ulf; Chinapirom, Teerapat; Rückert, Ulrich:
    Universal mini-robot with micro-processor and reconfigurable hardware.
    In: Proc. of FIRA RoboWorld Conference 2006, 2006. »»
    Abstract

    conference paper / id: 2289000

    Universal mini-robot with micro-processor and reconfigurable hardware

    Kaulmann, Tim; Witkowski, Ulf; Chinapirom, Teerapat; Rückert, Ulrich

    In this paper, a novel mini-robot is presented that features several new techniques concerning the chassis of the robot integrating electronic components, the usage of information processing principles and the robot's modularity. The core component for the information processing is a PCB integrating processor running Linux and a closely coupled FPGA offering partial reconfiguration of the FPGA resources for optimizing energy efficiency and computing resources.


    In: Proc. of FIRA RoboWorld Conference 2006, 2006.
  • Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Bhandare, Suhas; Ibrahim, Selwan K.; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold; Achiam, Y.:
    First Real-Time Data Recovery for SynchroneusQPSK Transmission with Standard DFB Lasers.
    In: IEEE PHOTONICS TECHNOLOGY LETTERS, Volume: 18, 2006. »»
    Abstract

    article / id: 2493726

    First Real-Time Data Recovery for SynchroneusQPSK Transmission with Standard DFB Lasers

    Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Bhandare, Suhas; Ibrahim, Selwan K.; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold; Achiam, Y.

    For the first time, synchronous quadrature phase-shift keying data is recovered in real-time after transmission with standard distributed feedback lasers using a digital inphase and quadrature receiver. Forward-error-correction-compatible performance is reached at 800 Mb/s after 63 km of fiber. Self-homodyne operation with an external cavity laser is error-free


    In: IEEE PHOTONICS TECHNOLOGY LETTERS, Volume: 18, 2006.
  • Paiz, Carlos; Pohl, Christopher; Porrmann, Mario:
    Reconfigurable Hardware in-the-Loop Simulations for Digital Control Design.
    In: 3th International Conference on Informatics in Control, Automation and Robotics (ICINCO), 2006. »»

    conference paper / id: 2494368

  • Tanoto, Andry; Du, Jia Lei; Witkowski, Ulf; Rückert, Ulrich:
    Teleworkbench: An Analysis Tool for Multi-Robotic Experiments.
    In: Proceedings of the IFIP Conference on Biologically Inspired Cooperative Computing (BICC 2006), 19th World Computer Congress (WCC), 2006. »»

    Teleworkbench: An Analysis Tool for Multi-Robotic Experiments

    Tanoto, Andry; Du, Jia Lei; Witkowski, Ulf; Rückert, Ulrich

    This paper presents a tool, one component of the Teleworkbench system, for analyzing experiments in multi-robotics. The proposed tool combines the video taken by a web cam monitoring the field where the experiment runs and some computer generated visual objects representing important events and information as well as robots’ behavior into one interactive video based on MPEG-4 standard. Visualization and data summarization enables the developer to quickly grasp a situation, whereas the possibility of scrolling through the video and selectively activating information helps him analyzing interesting events in depth. Because of the MPEG-4 standard used for the output video, the analysis process can be done in a wide range of platforms. This trait is beneficial for education and research cooperation purposes.


    In: Proceedings of the IFIP Conference on Biologically Inspired Cooperative Computing (BICC 2006), 19th World Computer Congress (WCC), 2006.
  • Griese, Björn; Kettelhoit, Boris; Porrmann, Mario:
    Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors.
    In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, 2006. »»
    Abstract

    conference paper / id: 2494374

    Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors

    Griese, Björn; Kettelhoit, Boris; Porrmann, Mario

    Dynamically reconfigurable FPGAs are well known to combine the flexibility of software with the performance of application specific hardware. As such they can be used as powerful but still flexible coprocessors in embedded processor systems. In this paper we analyze different variants for interfacing reconfigurable hardware from an embedded processor. We describe three different on-chip buses and evaluate their usability for dynamically reconfigurable systems. In addition, we analyze the communication latencies and the speed-up factor of a hardware accelerator for floating point operations for a total of eight different coupling variants


    In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, 2006.
  • Niemann, Jörg-Christian; Puttmann, Christoph; Porrmann, Mario; Rückert, Ulrich:
    GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications.
    In: ARCS'06 Architecture of Computing Systems, 2006. »»
    Abstract

    conference paper / id: 2288961

    GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications

    Niemann, Jörg-Christian; Puttmann, Christoph; Porrmann, Mario; Rückert, Ulrich

    In this paper, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before we are going to fabricate the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with disparate performance and throughput requirements at high reliability. Furthermore, the composition from predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators.


    In: ARCS'06 Architecture of Computing Systems, 2006.
  • Xu, Feng; Rückert, Ulrich:
    Neighborhood Discovery and MAC Protocol for MANETs using a Low Complexity Directional Scheme.
    In: Proceedings of World Mobile Congress (WMC’06), 2006. »»
    Abstract

    conference paper / id: 2289022

    Neighborhood Discovery and MAC Protocol for MANETs using a Low Complexity Directional Scheme

    Xu, Feng; Rückert, Ulrich

    Many MAC protocols for mobile ad hoc networks using directional communication have been proposed recently. However, the common deficiency of them is that their assumed directional schemes on the physical layer are very ideal so that such schemes are hard-to-implement or even infeasible for more terminals. In this paper, a CSMA/CA based MAC protocol is designed for our previously proposed low complexity directional scheme. The feasibility of this scheme has been adequately considered with respect to dimension, power consumption and hardware complexity.


    In: Proceedings of World Mobile Congress (WMC’06), 2006.
  • Hagemeyer, Jens; Kettelhoit, Boris; Porrmann, Mario:
    Dedicated Module Access in Dynamically Reconfigurable Systems.
    In: Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS), 2006. »»
    Abstract

    conference paper / id: 2473942

    Dedicated Module Access in Dynamically Reconfigurable Systems

    Hagemeyer, Jens; Kettelhoit, Boris; Porrmann, Mario

    Modern FPGAs, such as the Xilinx Virtex-II series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) during run-time. To enable communication with these modules and for controlling purposes, dedicated access to each module as well as dedicated signals to control the global communication are required. This paper discusses several ways of implementing dedicated signals and addresses the impact on dynamically reconfigurable systems. Two new approaches are introduced, which allow a permanent access to the modules and to the communication infrastructure even during reconfiguration


    In: Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS), 2006.
  • Hoffmann, Sebastian; Pfau, Timo; Adamczyk, Olaf; Peveling, Ralf; Porrmann, Mario; Noe, Reinhold:
    Hardware-Efficient and Phase Noise Tolerant Digital Synchronous QPSK Receiver Concept.
    In: Coherent Optical Technologies and Applications (COTA 2006), on CD, 2006. »»
    Fulltext (external) Abstract

    conference paper / id: 2494328

    Hardware-Efficient and Phase Noise Tolerant Digital Synchronous QPSK Receiver Concept

    Hoffmann, Sebastian; Pfau, Timo; Adamczyk, Olaf; Peveling, Ralf; Porrmann, Mario; Noe, Reinhold

    Simulation results and a first standard cell CMOS implementation are reported for efficient carrier and data recovery methods in the IF domain of digital I&Q receivers, for synchronous QPSK transmission with standard DFB lasers.


    In: Coherent Optical Technologies and Applications (COTA 2006), on CD, 2006.
  • Sauer, Christian; Gries, Matthias; Niemann, Jörg-Christian; Porrmann, Mario; Thies, Michael:
    Application-driven Development of Concurrent Packet Processing Platforms.
    In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, 2006. »»
    Fulltext (external) Abstract

    conference paper / id: 2494380

    Application-driven Development of Concurrent Packet Processing Platforms

    Sauer, Christian; Gries, Matthias; Niemann, Jörg-Christian; Porrmann, Mario; Thies, Michael

    We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we have to trade off flexibility against costs and performance. Our methodology therefore focuses on characterizing the application domain as early as possible. With this input, we can narrow the design space to one major design trajectory that starts with the most flexible solution and refines the platform architecture systematically to meet performance and costs constraints. Our flow includes an efficient path to implementation in hardware and software. The software implementation framework takes a modular application description and generates code for embedded processors that can easily be ported to different platforms and used for profiling. Different communication architectures, co-processors, and specializations of programmable processing elements can be derived from profiling results to affect the platform hardware. A DSL Access Multiplexer (DSLAM) is used as an example throughout the paper to depict the different phases of our design process.


    In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, 2006.
  • Paiz, Carlos; Chinapirom, Teerapat; Witkowski, Ulf; Porrmann, Mario:
    Dynamically Reconfigurable Hardware for Autonomous Mini-Robots.
    In: 32nd Annual Conference of the IEEE Industrial Electronics Society (IECON-2006), 2006. »»
    Abstract

    conference paper / id: 2494405

    Dynamically Reconfigurable Hardware for Autonomous Mini-Robots

    Paiz, Carlos; Chinapirom, Teerapat; Witkowski, Ulf; Porrmann, Mario

    Reconfigurable hardware (e.g., field programmable gate arrays - FPGAs) has been successfully used as processing units in various mini-robotic applications. In this work, we pursue to improve the utilization of reconfigurable hardware by introducing dynamic reconfiguration. A hardware-software architecture is presented, which enables the realization of dynamic reconfiguration for usage on autonomous mini-robots. Two application examples are presented. The first application is dealing with principles of reconfigurable digital controllers, the second is image processing in the context of robot vision. Platforms for the implementation of the principles are the mini-robot Khepera as well as a novel mini-robot providing dynamic reconfiguration and a chassis fabricated in MID technology for integrating mechanical and electrical components


    In: 32nd Annual Conference of the IEEE Industrial Electronics Society (IECON-2006), 2006.
  • Eickhoff, Ralf; Rückert, Ulrich:
    Robustness of Radial Basis Functions.
    In: Neurocomputing, 2006. »»
    Abstract

    conference paper / id: 2285694

    Robustness of Radial Basis Functions

    Eickhoff, Ralf; Rückert, Ulrich

    Neural networks are intended to be used in future nanoelectronic technology since these architectures seem to be robust to malfunctioning elements and noise in its inputs and parameters. In this work, the robustness of radial basis function networks is analyzed in order to operate in noisy and unreliable environment. Furthermore, upper bounds on the mean square error under noise contaminated parameters and inputs are determined if the network parameters are constrained. To achieve robuster neural network architectures fundamental methods are introduced to identify sensitive parameters and neurons.


    In: Neurocomputing, 2006.
  • Eickhoff, Ralf; Rückert, Ulrich:
    Pareto-optimal noise and approximation properties of RBFnetworks.
    In: Proceedings of the 16th International Conference on Artificial Neural Networks (ICANN), 2006. »»
    Abstract

    conference paper / id: 2289026

    Pareto-optimal noise and approximation properties of RBFnetworks

    Eickhoff, Ralf; Rückert, Ulrich

    Neural networks are intended to be robust to noise and tolerant to failures in their architecture. Therefore, these systems are particularly interesting to be integrated in hardware and to be operating under noisy environment. In this work, measurements are introduced which can decrease the sensitivity of Radial Basis Function networks to noise without any degradation in their approximation capability. For this purpose, pareto-optimal solutions are determined for the parameters of the network.


    In: Proceedings of the 16th International Conference on Artificial Neural Networks (ICANN), 2006.
  • Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Ibrahim, Selwan K.; Adamczyk, Olaf; Porrmann, Mario; Bhandare, Suhas; Noe, Reinhold; Achiam, Y.:
    Synchronous QPSK transmission at 1.6 Gbit/s with standard DFB lasers and real-time digital receiver.
    In: IEEE Electronic Letters, Volume: 42, 2006. »»
    Abstract

    article / id: 2493754

    Synchronous QPSK transmission at 1.6 Gbit/s with standard DFB lasers and real-time digital receiver

    Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Ibrahim, Selwan K.; Adamczyk, Olaf; Porrmann, Mario; Bhandare, Suhas; Noe, Reinhold; Achiam, Y.

    In a coherent and synchronous QPSK system with real-time data recovery and standard DFB lasers a data throughput of 1.6 Gbit=s is achieved, faster than ever reported. After 63 km of fibre the BER is well below the FEC threshold.


    In: IEEE Electronic Letters, Volume: 42, 2006.
  • Niemann, J.-C.; Sauer, C.; Porrmann, Mario; Rückert, Ulrich:
    Flexible Beschleunigungseinheit für die Verarbeitung von Datenpaketen.
    In: 2006. »»

    patent / id: 2494093

  • Hoffmann, Sebastian; Pfau, Timo; Peveling, Ralf; Bhandare, Suhas; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold:
    Synchrone 1,6-Gbits-QPSK-Datenübertragung in Echtzeit mit DFB-Lasern.
    In: Workshop der ITG Fachgruppe 5.3.1, Modellierung photonischer Komponenten und Systeme, 2006. »»

    conference paper / id: 2494346

  • Griese, Björn; Porrmann, Mario:
    A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems.
    In: Proceedings of the IFIP Conference on Biologically Inspired Cooperative Computing (BICC 2006), 2006. »»
    Abstract

    conference paper / id: 2494360

    A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems

    Griese, Björn; Porrmann, Mario

    Self-optimization is a promising approach to cope with the increasing complexity of today’s automation networks. The high complexity is mainly caused by a rising amount of network nodes and increasing real-time requirements. Dynamic hardware reconfiguration is a key technology for self-optimizing systems, enabling, e.g., Real-Time Communication Systems (RCOS) that adapt to varying requirements at runtime. Concerning dynamic reconfiguration of an RCOS, an important requirement is to maintain connections and to support time-constrained communication during reconfiguration. We have developed a dynamically reconfigurable Ethernet switch, which is the main building block of a prototypic implementation of an RCOS network node. Three methods for reconfiguring the Ethernet switch without packet loss are presented. A prototypical implementation of one method is described and analyzed in respect to performance and resource efficiency.


    In: Proceedings of the IFIP Conference on Biologically Inspired Cooperative Computing (BICC 2006), 2006.
  • Porrmann, Mario; Witkowski, U.; Rückert, Ulrich; Omondi, Amos; Rajapakse, Jagath:
    Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware.
    In: FPGA Implementations of Neural Networks, Springer-Verlag, 2006. »»
    Abstract

    book chapter / id: 2285718

    Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware

    Porrmann, Mario; Witkowski, U.; Rückert, Ulrich

    In this chapter we discuss an implementation of self-organizing feature maps in reconfigurable hardware. Based on the universal rapid prototyping system RAPTOR2000 a hardware accelerator for self-organizing feature maps has been developed. Using state of the art Xilinx FPGAs, RAPTOR2000 is capable of emulating hardware implementations with a complexity of more than 15 million system gates. RAPTOR2000 is linked to its host – a standard personal computer or workstation – via the PCI bus. For the simulation of self-organizing feature maps a module has been designed for the RAPTOR2000 system, that embodies an FPGA of the Xilinx Virtex (-E) series and optionally up to 128 MBytes of SDRAM. A speed-up of up to 190 is achieved with five FPGA modules on the RAPTOR2000 system compared to a software implementation on a state of the art personal computer for typical applications of self-organizing feature maps.


    In: FPGA Implementations of Neural Networks, Springer-Verlag, 2006.
  • Eickhoff, R.; Rückert, Ulrich:
    Enhancing Fault Tolerance of Radial Basis Functions.
    In: Neural Networks, 2006. IJCNN '06. International Joint Conference on, 2006. »»
    Abstract

    conference paper / id: 2286083

    Enhancing Fault Tolerance of Radial Basis Functions

    Eickhoff, R.; Rückert, Ulrich

    The challenge of future nanoelectronic applications, e.g. in quantum computing or in molecular computing, is to assure reliable computation facing a growing number of malfunctioning and failing computational units. Modeled on biology artificial neural networks are intended to be one preferred architecture for these applications because their architectures allow distributed information processing and, therefore, will result in tolerance to malfunctioning neurons and in robustness to noise. In this work, methods to enhance fault tolerance to permanently failing neurons of Radial Basis Function networks are investigated for function approximation applications. Therefore, a relevance measure is introduced which can be used to enhance the fault tolerance or, on the contrary, to control the network complexity if it is used for pruning.


    In: Neural Networks, 2006. IJCNN '06. International Joint Conference on, 2006.
  • Jäger, Björn; Porrmann, Mario; Rückert, Ulrich:
    Bio-inspired massively parallel architectures for nanotechnologies.
    In: Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS 2006)., 2006. »»
    Abstract

    conference paper / id: 2286278

    Bio-inspired massively parallel architectures for nanotechnologies

    Jäger, Björn; Porrmann, Mario; Rückert, Ulrich

    Massively parallel single-chip multiprocessors (CMP) share a number of traits with biological systems such as neural networks. These biological systems have therefore inspired a number of concepts that may help to overcome some of the problems that will come up in future circuit technologies. In this work we present a first comparison of CMPs based on processor cores of different complexity and estimate the efficiency of CMPs with regards to overall performance and energy consumption. The analysis is based on an analytical model of chip multiprocessing that can help to estimate the runtime and energy consumption of different parallel algorithms. As in previous work we will use the GigaNetIC architecture as a basis for the different CMP architectures


    In: Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS 2006)., 2006.
  • Eickhoff, R.; Kaulmann, T.; Rückert, Ulrich:
    SIRENS: A Simple Reconfigurable Neural Hardware Structure for artificial neural network implementations.
    In: Neural Networks, 2006. IJCNN '06. International Joint Conference on, 2006. »»
    Abstract

    conference paper / id: 2286350

    SIRENS: A Simple Reconfigurable Neural Hardware Structure for artificial neural network implementations

    Eickhoff, R.; Kaulmann, T.; Rückert, Ulrich

    Artificial neural networks are used in various applications and research areas. Mathematically inspired approaches use these types of networks to solve complex classification or function approximation tasks whereas biologically motivated models attempt to adapt desired properties from biology such as robustness or fault tolerance to technical systems and architectures. Therefore, a great variety of different models have been proposed in literature which can be separated in time-dependent and time-independent models. To verify these models and to accelerate simulations prototypes are often implemented in integrated circuits using digital or analog designs. In this work, a simple reconfigurable neural hardware structure (SIRENS) is introduced which is capable to represent several different models of neurons, time-independent and timedependent models as well. Therefore, this system can be used for several applications (classification or simulation) and purposes (acceleration or operation). The underlying mathematical principles are presented and, furthermore, design considerations are given in this paper.


    In: Neural Networks, 2006. IJCNN '06. International Joint Conference on, 2006.
  • Sauer, Christian; Gries, Matthias; Dirk, Sebastian; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich:
    A Lightweight NoC for the NOVA Packet Processing Plattform.
    In: Design, Automation and Test in Europe DATE, Future Interconnect and Network-on-Chip (NoC) Workshop, 2006. »»
    Fulltext (PDF) Fulltext (external)

    conference paper / id: 2288969

  • Eickhoff, Ralf; Sitte, Joaquin; Rückert, Ulrich:
    Robust Local Cluster Neural Networks (ESANN).
    In: Proceedings of the 14th European Symposium on Artificial Neural Networks (ESANN), 2006. »»

    Robust Local Cluster Neural Networks (ESANN)

    Eickhoff, Ralf; Sitte, Joaquin; Rückert, Ulrich

    Artificial neural networks are intended to be used in future nanoelectronics since their biological examples seem to be robust to noise. In this paper, we analyze the robustness of Local Cluster Neural Networks and determine upper bounds on the mean square error for noise contaminated weights and inputs.


    In: Proceedings of the 14th European Symposium on Artificial Neural Networks (ESANN), 2006.
  • Xu, Feng; Rückert, Ulrich:
    Neighborhood Discovery and MAC Protocol for MANETs using the Multiple-directional-antennas Scheme.
    In: Proceedings of VDE Kongress – ITG Fachtagung 'Mobility', 2006. »»

    conference paper / id: 2289018

  • Porrmann, Mario; Niemann, Jörg-Christian:
    Teaching Reconfigurable Computing Theory and Practice.
    In: International Workshop on Reconfigurable Computing Education (on CD), 2006. »»
    Abstract

    conference paper / id: 2494321

    Teaching Reconfigurable Computing Theory and Practice

    Porrmann, Mario; Niemann, Jörg-Christian

    Reconfigurable hardware is often used to enrich classical digital design and VLSI courses that target ASIC designs. In this way, students get a better feeling of what they are designing than when just looking at VHDL simulations. But teaching reconfigurable computing requires more than just examples of ASIC prototyping. Students need to get an in depth knowledge of the special features and requirements of reconfigurable architectures in order to be able to design reconfigurable systems that are coequal to ASIC or microprocessor based designs – not only in economics but also in performance and energy consumption. In this paper, we present two lectures that focus on reconfigurable computing and the associated labs, which range from simple CPLD designs to complex dynamically reconfigurable controllers with real-time requirements. During these courses our students gain step by step a broad insight into reconfigurable computing.


    In: International Workshop on Reconfigurable Computing Education (on CD), 2006.
  • Kalte, H.; Porrmann, Mario:
    REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAs.
    In: Proceedings of the 3rd Conference on Computing Frontiers, 2006. »»
    Fulltext (external) Abstract

    conference paper / id: 2494326

    REPLICA2Pro: Task Relocation by Bitstream Manipulation in VIRTEX-II/Pro FPGAs

    Kalte, H.; Porrmann, Mario

    One vision of dynamic hardware reconfiguration is to deliver virtually unlimited hardware resources to a set of hardware tasks implementing arbitrary functions. By using partial reconfiguration, these tasks can be allocated and de-allocated on the reconfigurable architecture while others continue to operate. However, the exact placement of each task can only be determined during runtime according to the current resource allocation. This requires relocating each task from its original position after place and route to an area of available resources. The process of relocating tasks can result in a major time overhead. In order to solve this problem we have developed the REPLICA2Pro (Relocation per online Configuration Alteration in Virtex-2/-Pro) filter, which is capable of performing task relocations by manipulating the task’s bitstream during the regular allocation process without any extra time overhead. The filter architecture, our reconfigurable system approach as well as our design flow and an experimental system setup are presented in this paper.


    In: Proceedings of the 3rd Conference on Computing Frontiers, 2006.
  • Koester, Markus; Kalte, Heiko; Porrmann, Mario:
    Relocation and Defragmentation for Heterogeneous Reconfigurable Systems.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '06), CSREA Press, 2006. »»
    Fulltext (external) Abstract

    conference paper / id: 2494340

    Relocation and Defragmentation for Heterogeneous Reconfigurable Systems

    Koester, Markus; Kalte, Heiko; Porrmann, Mario

    Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfiguration, arbitrary hardware tasks can be placed and removed at run-time, causing the free FPGA resources to become fragmented over time. This fragmentation can prevent a requested task from being placed, if the required FPGA resources are not available in a sufficiently large contiguous region. A solution to this problem is to relocate the currently placed tasks for being able to place the requested task. This paper introduces a run-time defragmentation algorithm, which relocates currently placed tasks on a heterogeneous FPGA area. Additionally, the necessary hardware mechanism for relocating a task at run-time are described. Simulation results for dynamically reconfiguring Xilinx Virtex-II FPGAs are presented, which show the improvement of the placement when using the proposed defragmentation algorithm. 1.


    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '06), CSREA Press, 2006.
  • Kettelhoit, Boris; Porrmann, Mario:
    A Layer Model for Systematically Designing Dynamically Reconfigurable Systems.
    In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications, 2006. »»
    Abstract

    conference paper / id: 2494364

    A Layer Model for Systematically Designing Dynamically Reconfigurable Systems

    Kettelhoit, Boris; Porrmann, Mario

    Partial and dynamic reconfiguration significantly enhances the potential of FPGAs, which has been shown in various prototypic implementations in the past. In this paper the authors introduce a new methodology that eases the design of dynamically reconfigurable systems. It is based on a layer model that systematically abstracts from the underlying reconfigurable hardware to the application that wants to use a dynamically loaded hardware module. With six specified layers and well defined interfaces between these layers we reduce the error-proneness of the system design while increasing the reusability of existing system components. The authors demonstrate the benefits of this design methodology with two example designs: a system-on-chip implementation and a multi-FPGA approach.


    In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications, 2006.
  • Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Bhandare, Suhas; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold; Achiam, Y.:
    1.6 Gbit/s Real-Time Synchronous QPSK Transmission with Standard DFB Lasers.
    In: Proceedings of the 32nd European Conference on Optical Communication (ECOC 2006), 2006. »»
    Abstract

    conference paper / id: 2494390

    1.6 Gbit/s Real-Time Synchronous QPSK Transmission with Standard DFB Lasers

    Pfau, Timo; Hoffmann, Sebastian; Peveling, Ralf; Bhandare, Suhas; Adamczyk, Olaf; Porrmann, Mario; Noe, Reinhold; Achiam, Y.

    Using standard DFB lasers, 1.6 Gbit/s QPSK data is demodulated and recovered coherently and synchronously in real-time, faster than ever before. BER after 63 km of fiber is well below the FEC threshold.


    In: Proceedings of the 32nd European Conference on Optical Communication (ECOC 2006), 2006.
2005
  • Kalte, Heiko; Kettelhoit, Boris; Koester, Markus; Porrmann, Mario; Rückert, Ulrich:
    A System Approach for Partially Reconfigurable Architectures.
    In: International Journal of Embedded Systems (IJES), Inderscience Publisher, Volume: 1, 2005. »»
    Abstract

    article / id: 2285654

    A System Approach for Partially Reconfigurable Architectures

    Kalte, Heiko; Kettelhoit, Boris; Koester, Markus; Porrmann, Mario; Rückert, Ulrich

    The increasing logic density of current Field Programmable Gate Arrays (FPGA) enables the integration of whole systems on one programmable chip. Using concepts of partial dynamic reconfiguration allows the adaptation of complex systems to changing requirements at run-time. In this paper we present a realisable approach for dynamic system integration on Xilinx Virtex FPGAs. In contrast to existing approaches that consider fixed slots for module placement, our approach allows fine-grained placement of modules with variable width along a horizontal communication infrastructure. By simulation we show that the proposed 1D-approach outperforms 2D-approaches by means of the device utilisation and external fragmentation.


    In: International Journal of Embedded Systems (IJES), Inderscience Publisher, Volume: 1, 2005.
  • Kalte, H.; Lee, G.; Porrmann, Mario; Rückert, Ulrich:
    REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems.
    In: Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD., 2005. »»
    Abstract

    conference paper / id: 2286119

    REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems

    Kalte, H.; Lee, G.; Porrmann, Mario; Rückert, Ulrich

    The feature of partial reconfiguration provided by currently available Field Programmable Gate Arrays (FPGAs) makes it possible to change hardware modules while others keep working. The combination of this feature and the high gate capacity enables the integration of dynamic systems that can be adapted to changing demands during runtime. Placing the dynamically changing modules along a horizontal communication infrastructure does not only provide communication facilities it also enables the relocation of pre-synthesized modules by bitstream manipulations. The exact placement of an incoming module is determined according to the current resource allocation, which results in an online placement problem. In order to prevent any extra configuration overhead for the relocation process, we developed the REPLICA (Relocation per online Configuration Alteration) filter, which is capable of performing the necessary bitstream manipulations during the regular download process. The filter architecture, a Configuration Manager and an evaluation example are presented in this paper.


    In: Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD., 2005.
  • Grosseschallau, M.; Witkowski, U.; Rückert, Ulrich:
    Low-cost Bluetooth Communication for the Autonomous Mobile Minirobot Khepera.
    In: Robotics and Automation, 2005. ICRA 2005. Proceedings of the 2005 IEEE International Conference on, 2005. »»
    Abstract

    conference paper / id: 2286284

    Low-cost Bluetooth Communication for the Autonomous Mobile Minirobot Khepera

    Grosseschallau, M.; Witkowski, U.; Rückert, Ulrich

    This paper presents a low-cost Bluetooth communication for autonomous mobile minirobots. The interfacing of the Bluetooth hardware is done by a simple UART connection, which makes the approach easily portable. Using ASCII commands and events, which are exchanged over this serial link, the Bluetooth operations can be controlled and monitored. Since internal Bluetooth stack operations are concealed, no deeper knowledge of the Bluetooth technology is necessary to utilize this wireless communication. These features make the presented approach perfectly suited for the integration into minirobots like the Khepera, where computational power and spatial resources are strictly limited.


    In: Robotics and Automation, 2005. ICRA 2005. Proceedings of the 2005 IEEE International Conference on, 2005.
  • Niemann, J.-G.; Porrmann, Mario; Rückert, Ulrich:
    A scalable parallel SoC architecture for network processors.
    In: VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on, 2005. »»
    Abstract

    conference paper / id: 2286309

    A scalable parallel SoC architecture for network processors

    Niemann, J.-G.; Porrmann, Mario; Rückert, Ulrich

    Information processing and networking of technical devices find their way into our daily life. In order to process the continuously growing quantity of data, powerful communication nodes for network processing are needed. We present an architecture for network processors that is based on a uniform, massively parallel structure. Thus, our approach takes advantage of reusing predefined IP building blocks. This leads to a short time to market, a high reliability and a scalable architecture. Our architecture is scalable to different areas of application by varying the number of integrated processors. Additionally, specific hardware accelerators can be embedded, which are optimized for the target application, in order to be especially resource-efficient in respect to power consumption, computational power and required area.


    In: VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on, 2005.
  • Kettelhoit, Boris; Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
    Dynamically Reconfigurable Hardware for Self-Optimizing Mechatronic Systems.
    In: 5. GMM/ITG/GI-Workshop Multi-Nature Systems, 2005. »»
    Abstract

    conference paper / id: 2288829

    Dynamically Reconfigurable Hardware for Self-Optimizing Mechatronic Systems

    Kettelhoit, Boris; Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich

    Reconfigurable hardware, and particularly field programmable gates arrays (FPGAs) allow the acceleration of digital control algorithm for mechatronic systems by exploiting their intrinsic parallelism. FPGAs also allow an efficient use of resources and flexible designs by using partial and dynamic reconfiguration. However, fully utilization of those benefits is often prevented by the necessary expertise to use such technology. In this paper a design flow for digital control algorithms using FPGAs is presented, which allows engineers without specialized knowledge on reconfigurable hardware design to use FPGAs as an implementation platform. We introduce a system architecture that enables the use of partially dynamic reconfiguration of FPGAs as part of our design flow and show an implementation example using an inverted pendulum system.


    In: 5. GMM/ITG/GI-Workshop Multi-Nature Systems, 2005.
  • Grünewald, Matthias; Xu, Feng; Rückert, Ulrich:
    Increasing the Resource-Efficiency of the CSMA/CA Protocol in Directional Ad Hoc Networks.
    In: Proceedings of the 4th International Conference on AD-HOCNetworks & Wireless, 2005. »»
    Abstract

    conference paper / id: 2288843

    Increasing the Resource-Efficiency of the CSMA/CA Protocol in Directional Ad Hoc Networks

    Grünewald, Matthias; Xu, Feng; Rückert, Ulrich

    The use of directional communication can result in higher performance of ad hoc networks in terms of throughput and delay. To exploit these advantages, we propose a system architecture that applies k air interfaces on each node. Each interface is equipped with a directional antenna. However, the energy consumption of such a system would be too high intuitionally. Power management is required that switches off the air interfaces if they are not needed. Hence, we design a detailed energy model for the system and a MAC protocol based on CSMA/CA with extensions for parallel directional communication, radiation power control and air interface power management. We verify and evaluate our implementation in a simulation environment. Our results show that the proposed system can achieve an energy efficiency comparable to a single antenna system while increasing the throughput and time efficiency of the resulting ad hoc network by a factor of 2-3.


    In: Proceedings of the 4th International Conference on AD-HOCNetworks & Wireless, 2005.
  • Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich:
    Dynamic Reconfiguration of Universal FPGA-Microcontroller Module.
    In: FIRA RoboWorld Congress 2005, 2005. »»
    Abstract

    conference paper / id: 2288920

    Dynamic Reconfiguration of Universal FPGA-Microcontroller Module

    Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich

    This paper presents dynamic reconfiguration of FPGA hardware for mini-robots. By dynamic reconfiguration the robot's hardware can be optimally utilized depending on the application context. The application considered in this paper is robot soccer. For this, the autonomous mini-robot Khepera is equipped with 2D camera and our universal FPGA-Microcontroller module.


    In: FIRA RoboWorld Congress 2005, 2005.
  • Franzmeier, Marc; Rückert, Ulrich; Witkowski, Ulf; Cabestany, J.; Prieto, A.; Sandoval, D.F.:
    Explorative Data Analysis Based on Self-Organizing Maps and Automatic Map Analysis.
    In: Proceedings of the 8th International Work-Conference on Artificial Neural Networks (IWANN), 2005. »»

    Explorative Data Analysis Based on Self-Organizing Maps and Automatic Map Analysis

    Franzmeier, Marc; Rückert, Ulrich; Witkowski, Ulf

    In the field of explorative data analysis self-organizing maps have been used successfully for a lot of applications. In our case, we apply the self-organizing map for the analysis of semiconductor fabrication data by training recorded high dimensional data sets. Usually, the training result is displayed by using appropriate visualization techniques and the results are evaluated manually. Especially for large data sets an automated post-processing of the training result is essential. In this paper an automatic training result analysis based on specific image processing is introduced. Dependencies between components maps are calculated by structure overlapping analysis based on the segmentation of component maps. This novel method has been integrated into the data analysis software DanI, that simulates self-organizing maps for data analysis with several pre-processing and post-processing capabilities.


    In: Proceedings of the 8th International Work-Conference on Artificial Neural Networks (IWANN), 2005.
  • Paiz, C.; Kettelhoit, B.; Klassen, A.; Porrmann, Mario; Rückert, Ulrich:
    Dynamically reconfigurable hardware for digital controllers in mechatronic systems.
    In: IEEE International Conference on Mechatronics (ICM 2005), 2005. »»
    Abstract

    conference paper / id: 2288944

    Dynamically reconfigurable hardware for digital controllers in mechatronic systems

    Paiz, C.; Kettelhoit, B.; Klassen, A.; Porrmann, Mario; Rückert, Ulrich

    Reconfigurable hardware, and particularly field programmable gates arrays (FPGAs) allow the acceleration of digital control algorithm for mechatronic systems by exploiting their intrinsic parallelism. FPGAs also allow an efficient use of resources and flexible designs by using partial and dynamic reconfiguration. However, fully utilization of those benefits is often prevented by the necessary expertise to use such technology. In this paper a design flow for digital control algorithms using FPGAs is presented, which allows engineers without specialized knowledge on reconfigurable hardware design to use FPGAs as an implementation platform. We introduce a system architecture that enables the use of partially dynamic reconfiguration of FPGAs as part of our design flow and show an implementation example using an inverted pendulum system.


    In: IEEE International Conference on Mechatronics (ICM 2005), 2005.
  • Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich:
    Universal FPGA-Microcontroller Module for Autonomous Minirobots.
    In: AMiRE, 2005. »»
    Abstract

    conference paper / id: 2288955

    Universal FPGA-Microcontroller Module for Autonomous Minirobots

    Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich

    This paper presents an extension turret for efficient data processing for autonomous minirobots, in particular the minirobot Khepera. The Khepera robot is a base platform of a mobile autonomous system for our experiments, but the robot’s main processor cannot accomplish complex processing tasks with real-time requirements, because of the processor’s low performance. Thus, we have designed an extension hardware module based on a field programmable gate array (FPGA) to run the real-time processing and concurrently control other peripheral modules. The module with coupling of FPGA and a microcontroller gains robot’s ability and possesses FPGA’ flexibility of reconfiguration.


    In: AMiRE, 2005.
  • Rückert, Ulrich:
    Abschlußbericht zum Projekt: Aktives Nachsichtsystem für mehr Sicherheit im Straßenverkehr.
    In: Heinz Nixdorf Institut, Universität Paderborn, 2005. »»

    report / id: 2285785

  • Koester, M.; Porrmann, Mario; Rückert, Ulrich:
    Placement-Oriented Modeling of Partially Reconfigurable Architectures.
    In: Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD., 2005. »»
    Fulltext (external) Abstract

    conference paper / id: 2286050

    Placement-Oriented Modeling of Partially Reconfigurable Architectures

    Koester, M.; Porrmann, Mario; Rückert, Ulrich

    Dynamic reconfiguration is a promising approach for resource efficient utilization of microelectronic systems. However, work on general approaches to model reconfigurable hardware is quite rare. Therefore, we have developed a new analytical model, which can be used for the analysis of the various approaches to dynamic reconfiguration. Based on our model we define metrics for partial reconfiguration to evaluate different system approaches. Our main objective is to analyze placement algorithms for partially reconfigurable architectures. The model is able to consider miscellaneous constraints and cost parameters for online placement. Thus, placement can be adapted to dynamically changing system environments.


    In: Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005) - Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, on CD., 2005.
  • Du, Jia Lei; Witkowski, U.; Rückert, Ulrich:
    CSD: cell-based service discovery in large-scale robot networks.
    In: Intelligent Robots and Systems, 2005. (IROS 2005). 2005 IEEE/RSJ International Conference on, 2005. »»
    Abstract

    conference paper / id: 2286202

    CSD: cell-based service discovery in large-scale robot networks

    Du, Jia Lei; Witkowski, U.; Rückert, Ulrich

    If robots are deployed in large numbers in our environment in future, collaboration between the presumably specialized robots will be essential for a successful operation. The robots will set up mobile ad-hoc networks for communication and efficient routing and discovery protocols for such robot networks will provide the basic layer for a successful collaboration of the robots. In this paper we present a service discovery protocol that allows robots to efficiently discover available services in the network. It is specifically designed for large-scale robot networks. It takes into account the high dynamics of robot networks and exploits the position data of the robots to increase scalability and efficiency. A cellbased grid with master nodes in each cell forms the basic structure. Through proactive intra-cell communication and reactive inter-cell communication, scalability is ensured and the effects of node movements on the overall network are minimized. We implemented our solution in an example scenario.


    In: Intelligent Robots and Systems, 2005. (IROS 2005). 2005 IEEE/RSJ International Conference on, 2005.
  • Tanoto, Andry; Witkowski, Ulf; Rückert, Ulrich:
    Teleworkbench: A Teleoperated Platform for Multi-Robot Experiments.
    In: Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE 2005), 2005. »»
    Abstract

    conference paper / id: 2288816

    Teleworkbench: A Teleoperated Platform for Multi-Robot Experiments

    Tanoto, Andry; Witkowski, Ulf; Rückert, Ulrich

    Robot development is a highly complex and interdisciplinary process. It comprises several phases: design, implementation, as well as test and validation to name some of them. In test and validation, simulation is commonly used. However, experiments with real robots still have a very important role since simulations cannot accurately model the real environment and, as a result, produce inconclusive results [1]. Performing robotic experiments, however, is considerably tedious. It is a repetitive process consisting of several steps: setup, execution, data logging, monitoring, and analysis. Moreover, it also requires a lot of resources especially in the case of experiments in multi-robotics. We have designed a system that can ease the tasks of performing experiments with single or multi minirobots, called the Teleworkbench [2]. The aim of the system is to provide a standard environment in which algorithms and programs can be tested and validated using real robots. As they run in a standardized environment, benchmarking in robotics can be achieved. Also there are several reasons to choose minirobots: the small-size, low-complexity, and low-cost to name a few. Moreover, it is easy to scale up developed solutions for minirobots to larger platforms or to scale them down to micro-mechanical systems (MEMS).


    In: Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE 2005), 2005.
  • Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich:
    Sensornahe Signalverarbeitung mit FPGAs am Beispiel der Berechnung des optischen Flusses auf mobilen Robotern.
    In: 3. Paderborner Workshop: Intelligente Mechatronische Systeme, 2005. »»
    Abstract

    conference paper / id: 2288823

    Sensornahe Signalverarbeitung mit FPGAs am Beispiel der Berechnung des optischen Flusses auf mobilen Robotern

    Chinapirom, Teerapat; Witkowski, Ulf; Rückert, Ulrich

    Inhalt des Artikels ist die sensornahe Informationsverarbeitung von Sensordaten mit FPGAs. Die enge Kopplung von Sensoren und FPGA-Bausteinen erlaubt sowohl die flexible Ansteuerung von Sensoren über eine Vielzahl von IO-Schnittstellen, als auch die Verarbeitung der aufgenommenen Sensorsignale. Aufgrund der sensornahen Informationsverarbeitung werden i.A. keine großen Datenmengen an einen zentralen Prozessor übertragen, dieser Prozessor wird entlastet, der Verdrahtungsaufwand zwischen Sensoren und zentralem Prozessor fällt geringer aus und die Störanfälligkeit kann reduziert werden.


    In: 3. Paderborner Workshop: Intelligente Mechatronische Systeme, 2005.
  • Kaulmann, Tim; Ferber, Markus; Witkowski, Ulf; Rückert, Ulrich; Cabestany, J.; Prieto, A.; Sandoval, D.F.:
    Analog VLSI Implementation of Adaptive Synapses in Pulsed Neural Networks.
    In: Proceedings of the 8th International Work-Conference on Artificial Neural Networks (IWANN), 2005. »»
    Abstract

    conference paper / id: 2288861

    Analog VLSI Implementation of Adaptive Synapses in Pulsed Neural Networks

    Kaulmann, Tim; Ferber, Markus; Witkowski, Ulf; Rückert, Ulrich

    An analog VLSI implementation of adaptive synapses being part of an associative memory realised with pulsed neurons is presented. VLSI implementations of dynamic synapses and pulsed neurons are expected to provide robustness and low energy consumption like observed in the human brain. We have developed a VLSI implementation of synaptic connections for an associative memory which is used in a biological inspired image processing system using pulse coded neural networks. The system consists of different layers for feature extraction to decompose the image in several features. The pulsed associative memory is used for completing or binding features. In this paper, we focus on the dynamics and the analog implementation of adaptive synapses. The discussed circuits were designed in a 130 nm CMOS process.


    In: Proceedings of the 8th International Work-Conference on Artificial Neural Networks (IWANN), 2005.
  • Kettelhoit, Boris; Klassen, Alexander; Paiz, Carlos; Porrmann, Mario; Rückert, Ulrich:
    Rekonfigurierbare Hardware zur Regelung mechatronischer Systeme.
    In: 3. Paderborner Workshop: Intelligente mechatronische Systeme, 2005. »»
    Abstract

    conference paper / id: 2288900

    Rekonfigurierbare Hardware zur Regelung mechatronischer Systeme

    Kettelhoit, Boris; Klassen, Alexander; Paiz, Carlos; Porrmann, Mario; Rückert, Ulrich

    Trotz ihrer hohen Leistungsfähigkeit leiden digitale Hardware-Lösungen für Re-gelungen in mechatronischen Systemen oft darunter, dass für ihren Einsatz detaillierte Kenntnisse im Entwurf digitaler Schaltungen erforderlich sind. Zusätzlich sind sie im Vergleich zu den meist favorisierten Mikrokontroller- oder DSP-Lösungen wenig flexibel. In diesem Beitrag wird eine Systemarchitektur vorgestellt, die mit Hilfe dynamisch rekonfigurierbarer Hardware ein ähnliches Maß an Flexibilität wie DSPs erreicht, ohne dabei an Leistungsfähigkeit einzubüßen. Darüber hinaus beschreiben wir einen Entwurfsprozess, der es einem Entwickler auch ohne tiefgehende Hardware-Kenntnisse ermöglicht, mit gewohnten Entwicklungsumgebungen Hardware-Regelungen zu realisieren.


    In: 3. Paderborner Workshop: Intelligente mechatronische Systeme, 2005.
  • Koester, Markus; Kalte, Heiko; Porrmann, Mario:
    Task Placement for Heterogeneous Reconfigurable Architectures.
    In: Proceedings of the IEEE 2005 Conference on Field-Programmable Technology (FPT '05), 2005. »»
    Abstract

    conference paper / id: 2494437

    Task Placement for Heterogeneous Reconfigurable Architectures

    Koester, Markus; Kalte, Heiko; Porrmann, Mario

    The concept of partial reconfiguration offers the possibility to dynamically place and remove hardware tasks on reconfigurable architectures, like FPGAs. Common placement algorithms, e.g. Best Fit, are designed for homogeneous architectures, since they do not consider any placement constraints of the hardware tasks. Due to the integration of, e.g., dedicated memory, current FPGAs are heterogeneous reconfigurable architectures. In this paper we introduce two heterogeneous placement algorithms, which are able to deal with the constraints of the hardware tasks. Both algorithms are compared to the Best Fit algorithm by using a simulation framework for partially configurable architectures. We propose concepts of an efficient hardware realization of our placement approach with Xilinx Virtex-II FPGAs. Moreover, we present a task placement mechanism to change the position of a hardware task on the FPGA by manipulating the configuration data of the task


    In: Proceedings of the IEEE 2005 Conference on Field-Programmable Technology (FPT '05), 2005.
  • Grünewald, Matthias; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich; Crowely, Patrick; Franklin, Mark A.; Hadimioglu, Haldun; Onufryk, Peter Z.:
    A framework for design space exploration of resource efficient network processing on multiprocessor SoCs.
    In: Network Processor Design: Issues and Practices, Volume: 3, Morgan Kaufmann Publisher, 2005. »»

    book chapter / id: 2145286

  • Xu, Feng; Grunewald, M.; Rückert, Ulrich:
    A low complexity directional scheme for mobile ad hoc networks.
    In: Personal, Indoor and Mobile Radio Communications, 2005. PIMRC 2005. IEEE 16th International Symposium on, Volume: 2, 2005. »»
    Fulltext (external) Abstract

    conference paper / id: 2285950

    A low complexity directional scheme for mobile ad hoc networks

    Xu, Feng; Grunewald, M.; Rückert, Ulrich

    In the context of single frequency band and omnidirectional communication, the throughput of wireless network is interference limited. Collision may occur if other signals impinge the destination while it is receiving the intended signal. To prevent collisions, CSMAICA is applied to serialize the communication tasks. Recently, numerous directional schemes have been proposed to further increase the network throughput. In this paper, a practical scheme for directional communication based on a simplified switched beam technique is proposed on the physical layer. Additionally, the corresponding modifications on the CSMA/CA protocol are also studied to optimize the overall system performance. It is worthy of notice that this scheme is feasible for the mobile portable device under state-ofthe- art technologies in terms of dimension, power consumption, hardware complexity and computing requirements. Preliminary simulations show that this scheme can increase the network throughput up to two times compared to an omni-directional system at the cost of only 10% higher power consumption.


    In: Personal, Indoor and Mobile Radio Communications, 2005. PIMRC 2005. IEEE 16th International Symposium on, Volume: 2, 2005.
  • Niemann, Jörg-Christian; Porrmann, Mario; Sauer, Christian; Rückert, Ulrich:
    An Evaluation of the Scalable GigaNetIC Architecture for Access Networks.
    In: Advanced Networking and Communications Hardware Workshop (ANCHOR), held in conjunction with the 32nd Annual International Symposium on Computer Architecture (ISCA 2005), 2005. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2288853

    An Evaluation of the Scalable GigaNetIC Architecture for Access Networks

    Niemann, Jörg-Christian; Porrmann, Mario; Sauer, Christian; Rückert, Ulrich

    We present an architecture for network processing nodes based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a range of packet processing applications with disparate performance and throughput requirements at high reliability. Furthermore, the composition from predefined building blocks guarantees fast design cycles and eases system verification. For particular resource efficiency in terms of power consumption, computational performance, and area requirements, specialized hardware accelerators can be embedded into the tailored processor cluster, which have been optimized for a particular target application. We demonstrate our approach using a real-world network access scenario that implements a full Internet protocol based digital subscriber line access multiplexer (IP-DSLAM) on our architecture. For this scenario, we achieve substantial increases of performance with only a slight area increase of less than 0.3 %. At the same time, the processors are strongly relieved and are thus available for the remaining tasks.


    In: Advanced Networking and Communications Hardware Workshop (ANCHOR), held in conjunction with the 32nd Annual International Symposium on Computer Architecture (ISCA 2005), 2005.
  • Griese, Björn; Oberthür, Simon; Porrmann, Mario; Rettberg, Achim; Zanella, Mauro C.; Rammig, Franz Josef:
    Component case study of a self-optimizing RCOS/RTOS system: A reconfigurable network service.
    In: From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), 2005. »»
    Fulltext (external) Abstract

    conference paper / id: 2494412

    Component case study of a self-optimizing RCOS/RTOS system: A reconfigurable network service

    Griese, Björn; Oberthür, Simon; Porrmann, Mario

    In highly dynamic scenarios a real-time communication/real-time operating system (RCOS/RTOS), which can fulfill all upcoming demands of the application, is normally very extensive. These RCOS/RTOS systems are heavy-weighted and produce much overhead. System resources for an application or a system service are often reserved for worst-case scenarios and are not usable for other applications. We present a self-optimizing RCOS/RTOS with an integrated flexible resource management. Our RCOS/RTOS adapts its services to the application demands and redistributes temporarily unused resources to other applications under hard real-time conditions. The benefit of our system is shown by means of a self-optimizing communication service. The main building block of this communication service is a reconfigurable dual-port Ethernet switch. Using dynamically reconfigurable hardware to implement the switch enables an adaption of the switch to changing requirements during run-time.


    In: From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), 2005.
  • Kalte, Heiko; Porrmann, Mario:
    Context Saving and Restoring for Multitasking in Reconfigurable Systems.
    In: 15th International Conference on Field Programmable Logic and Applications, 2005. »»
    Abstract

    conference paper / id: 2494424

    Context Saving and Restoring for Multitasking in Reconfigurable Systems

    Kalte, Heiko; Porrmann, Mario

    Today's Field Programmable Gate Arrays (FPGAs) can be reconfigured partially, which makes it possible to share resources between various functional modules (hardware tasks) over time. This concept is well known in the area of conventional operating systems. However, in order to transfer resource sharing concepts to operating systems on FPGAs, several underlying mechanisms have to be developed. One of these mechanisms is to suspend hardware tasks and restart them at another time and/or another area of the FPGA. Addressing this problem, this paper discusses ways to save and restore the state information of a hardware task. Afterwards, an implementation of a state relocation mechanisms is presented that uses the standard configuration port. In contrast to similar approaches, we significantly reduce the amount of readback data by reading only those configuration frames that contain state information. We finally determine the time overhead for task relocation, which is essential for most multitasking concepts, like defragmentation.


    In: 15th International Conference on Field Programmable Logic and Applications, 2005.
  • Koester, Markus; Kalte, Heiko; Porrmann, Mario:
    Run-Time Defragmentation for Partially Reconfigurable Systems.
    In: Proceedings of the International Conference on Very Large Scale Integration (IFIP VLSI-SOC), 2005. »»

    conference paper / id: 2494429

  • Du, Jia Lei; Ruhrup, S.; Witkowski, U.; Rückert, Ulrich:
    Resource and service discovery for large-scale robot networks in disaster scenarios.
    In: Safety, Security and Rescue Robotics, Workshop, 2005 IEEE International, 2005. »»
    Abstract

    conference paper / id: 2285904

    Resource and service discovery for large-scale robot networks in disaster scenarios

    Du, Jia Lei; Ruhrup, S.; Witkowski, U.; Rückert, Ulrich

    If robots are deployed in large numbers in disaster scenarios, the ability to discover and exchange resources and services with other robots in an open, heterogeneous, large-scale network will be essential for a successful operation. In this paper we present a discovery protocol that enables robots to efficiently locate resources and services available in large-scale networks. It is specifically designed for robot networks which are characterized by potentially highly dynamic network topologies and high service announcement-to-lookup ratios. The protocol exploits the position data of the robots to increase scalability and efficiency. A cell-based overlay structure is created, with master nodes in each cell. Through proactive intra-cell communication and reactive inter-cell communication, scalability is ensured and the effects of node movements on the overall network are minimized.


    In: Safety, Security and Rescue Robotics, Workshop, 2005 IEEE International, 2005.
  • Liß, Christian; Peveling, Ralf; Porrmann, Mario; Rückert, Ulrich:
    Technologieplanung in der Mikroelektronik – von Moore's Law zur Nanotechnologie-Roadmap.
    In: Symposium fuer Vorausschau und Technologieplanung, 2005. »»

    conference paper / id: 2288910

  • Rückert, Ulrich; Beiu, Valeriu:
    Neural Inspired Architectures for Nanoelectronics.
    In: Second International Conference on intelligent Computing and Information Systems – ICICIS 2005, 2005. »»
    Abstract

    conference paper / id: 2288927

    Neural Inspired Architectures for Nanoelectronics

    Rückert, Ulrich; Beiu, Valeriu

    Extremely down-scaled field effect transistor, innovative manufacturing of semiconductors, novel material and computing devices have led to rapid changes in the semiconductor industry which now allows more complex systems and more computing power per chip area than several years ago. Albeit these significant improvements novel technology nodes also offer unsolved problems to researchers and challenges to the designers. In this paper, we give a brief overview about actual trends and problems in the semiconductor industry and how the upcoming tasks can be solved by the designers and researchers.


    In: Second International Conference on intelligent Computing and Information Systems – ICICIS 2005, 2005.
  • Eickhoff, R.; Rückert, Ulrich:
    Fault-tolerance of basis function networks using tensor product stabilizers.
    In: Systems, Man and Cybernetics, 2005 IEEE International Conference on, Volume: 3, 2005. »»
    Abstract

    conference paper / id: 2286007

    Fault-tolerance of basis function networks using tensor product stabilizers

    Eickhoff, R.; Rückert, Ulrich

    Neural networks are intended to be used in future nanoelectronics since these architectures seem to be fault-tolerant to malfunctioning elements and robust to noise. In this paper, the robustness to noise of Basis Function networks using tensor product stabilizers is analyzed and upper bounds of the mean square error under noise contaminated weights or inputs are determined. Furthermore, consequences of permanently malfunctioning neurons are investigated and their impact on the mean squared error is analyzed. To achieve a reliable operation of the neural network necessary restrictions are introduced. Finally, the impact of technical realizations is investigated and its complexity is compared to Radial Basis Functions.


    In: Systems, Man and Cybernetics, 2005 IEEE International Conference on, Volume: 3, 2005.
  • Jager, B.; Niemann, J.-C.; Rückert, Ulrich:
    Analytical approach to massively parallel architectures for nanotechnologies.
    In: Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on, 2005. »»
    Abstract

    conference paper / id: 2286292

    Analytical approach to massively parallel architectures for nanotechnologies

    Jager, B.; Niemann, J.-C.; Rückert, Ulrich

    In the emerging field of single-chip multiprocessors (CMP) analytical models of performance and power consumption are necessary for design space exploration and the analysis of existing architectures. In the light of ever decreasing structure sizes in microchips the scalability of proposed CMPs is of great interest to the developers. Looking even further into the future at the possibilities offered by, e. g., nanotechnology, a set of such models may help to identify promising architectures and possible bottlenecks even before the enabling technologies exist. In this paper, we present our current work in this area in the form of two models. The first and very basic model is based on Amdahl’s law and gives a first promising outlook on chip multiprocessing. Based on the more complex BSP model our second model takes the on-chip communication into account and thus allows a much more detailed look at the architecture. In both cases, basic laws of circuit technology have been combined with the underlying models that now take the effects of device scaling into account. Later we will also present the GigaNetIC 1 architecture, a CMP developed by our research group. It will then be analyzed by applying the BSP-based model.


    In: Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on, 2005.
  • Eickhoff, Ralf; Rückert, Ulrich; Cabestany, J.; Prieto, A.; Sandoval, D.F.:
    Robustness of Radial Basis Functions.
    In: Proceedings of the 8th International Work-Conference on Artificial Neural Networks (IWANN), 2005. »»
    Abstract

    conference paper / id: 2288806

    Robustness of Radial Basis Functions

    Eickhoff, Ralf; Rückert, Ulrich

    Neural networks are intended to be used in future nanoelectronic technology since these architectures seem to be robust to malfunctioning elements and noise in its inputs and parameters. In this work, the robustness of radial basis function networks is analyzed in order to operate in noisy and unreliable environment. Furthermore, upper bounds on the mean square error under noise contaminated parameters and inputs are determined if the network parameters are constrained. To achieve robuster neural network architectures fundamental methods are introduced to identify sensitive parameters and neurons.


    In: Proceedings of the 8th International Work-Conference on Artificial Neural Networks (IWANN), 2005.
  • Eickhoff, Ralf; Rückert, Ulrich:
    Tolerance of Radial-Basis Functions Against Stuck-At-Faults.
    In: Proceedings of the International Conference on Artificial Neural Networks (ICANN), 2005. »»

    Tolerance of Radial-Basis Functions Against Stuck-At-Faults

    Eickhoff, Ralf; Rückert, Ulrich

    Neural networks are intended to be used in future nanoelectronic systems since neural architectures seem to be robust against malfunctioning elements and noise in their weights. In this paper we analyze the fault-tolerance of Radial Basis Function networks to Stuck- At-Faults at the trained weights and at the output of neurons. Moreover, we determine upper bounds on the mean square error arising from these faults.


    In: Proceedings of the International Conference on Artificial Neural Networks (ICANN), 2005.
  • Du, Jia Lei; Witkowski, Ulf; Rückert, Ulrich:
    Teleoperation of a Mobile Autonomous Robot using Web Services.
    In: Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE 2005), 2005. »»
    Abstract

    conference paper / id: 2288875

    Teleoperation of a Mobile Autonomous Robot using Web Services

    Du, Jia Lei; Witkowski, Ulf; Rückert, Ulrich

    A web service is a web-based application that allows client programs to access its functionality using open, standardized protocols. This approach ensures interconnectivity and interoperability so that the functionality of the web service can be accessed by virtually any client, regardless of location and programming language or platform. Autonomous mobile robots have the ability to perceive and physically interact with the real world. The ability of physical manipulation would fundamentally extend the service capability of web services. On the other hand, by equipping mobile autonomous robots with web service interfaces, a standardized, interoperable way for world-wide access to the robots could be provided. In this project we study the suitability of the web service standards and technologies for the teleoperation of mobile autonomous robots. As project result we provide access to a mobile autonomous robot via a web service interface.


    In: Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE 2005), 2005.
  • Eickhoff, Ralf; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich; Rettberg, Achim; Zanella, Mauro C.; Rammig, Franz Josef:
    Adaptable Switch boxes as on-chip routing nodes for networks-on-chip.
    In: From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), 2005. »»

    Adaptable Switch boxes as on-chip routing nodes for networks-on-chip

    Eickhoff, Ralf; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich

    Due to continuous advancements in modern technology processes which have resulted in integrated circuits with smaller feature sizes and higher complexity, current system-on-chip designs consist of many different components such as memories, interfaces and microprocessors. To handle this growing number of components, an efficient communication structure must be provided and incorporated during system design. This work deals with the implementation of an efficient communication structure for an on-chip multiprocessor design. The internal structure of one node is proposed and specified by its requirements. Furthermore, different routing strategies are implemented. Moreover, the communication structure is mapped on a standard cell process to examine the achieved processing speed and to determine the area requirements.


    In: From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), 2005.
2004
  • Rückert, Ulrich:
    Abschlußbericht zum BMBF-Projekt: GigaNet-IC: Netzwerktechnik der nächsten Generation.
    In: Heinz Nixdorf Institut, Universität Paderborn, 2004. »»

    report / id: 2285779

  • Loeser, C.; Brinkmann, A.; Rückert, Ulrich:
    Distributed path selection (DPS) a traffic engineering protocol for IP-networks.
    In: System Sciences, 2004. Proceedings of the 37th Annual Hawaii International Conference on, 2004. »»
    Abstract

    conference paper / id: 2286044

    Distributed path selection (DPS) a traffic engineering protocol for IP-networks

    Loeser, C.; Brinkmann, A.; Rückert, Ulrich

    The path selection strategy of an autonomous system (AS) has got a strong impact on the latency of packets travelling through the AS and the throughput of the underlying network. In theoretical analysis it has been shown for a simple load balancing approach that it can achieve a near optimal packet throughput even in the case of a dynamically changing network and for adversarial packet injections. Similar results have not been shown for any other protocol. The drawbacks of this load balancing approach are that it requires a large amount of information that has to be spread among the network, that it does not detect the drop out of nodes, and that it requires a complex buffer management. In this paper we examine the new routing protocol DPS (Distributed Path Selection) that is based on this simple load balancing approach. DPS overcomes its restrictions by the use of new protocol enhancements and is able to transfer the optimal properties of the load balancing approach into a routing protocol. Comparing DPS with OSPF and RIP by simulation, we will show that DPS is able to significantly improve the properties of the path system by considering the network topology as well as the traffic pattern while calculating the path system in a reasonable amount of time.


    In: System Sciences, 2004. Proceedings of the 37th Annual Hawaii International Conference on, 2004.
  • Pohl, C.; Franzmeier, M.; Porrmann, Mario; Rückert, Ulrich:
    gNBX - reconfigurable hardware acceleration of self-organizing maps.
    In: Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, 2004. »»
    Abstract

    conference paper / id: 2286138

    gNBX - reconfigurable hardware acceleration of self-organizing maps

    Pohl, C.; Franzmeier, M.; Porrmann, Mario; Rückert, Ulrich

    In this paper a new FPGA based hardware accelerator (gNBX) for Se(f-Organizing Maps is introduced. New principles for hardware acceleration of Self-Organizing Maps, which increase the degree of paralleliry arid therefore the acceleration gain will be presented. Our technology independent design description can be mapped on application specific integrated circuits if very high performance is required, as well as on Field Programmable Gate Arrays (FPGAS). which offer mid level performance (a speed up factor of up to 70 in comparison with PCs for t)pical datasets is achieved) at relativly low costs. Additional),, FPGAs offer the jlexibility to adapt the hardware to the changing requirements of the application during runtime. Therefore, the hardware can be exploited optimally at all times during the simulati011 process. Several benchmark scenarios with well known datasets will show rheperforniance of our system.


    In: Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, 2004.
  • Kalte, Heiko; Koester, Markus; Kettelhoit, Boris; Porrmann, Mario; Rückert, Ulrich; Plaks, Toomas:
    A Comparative Study on System Approaches for Partially Reconfigurable Architectures.
    In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '04), CSREA Press, 2004. »»

    conference paper / id: 2288730

  • Griese, Björn; Vonnahme, Erik; Porrmann, Mario; Rückert, Ulrich:
    Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures.
    In: Proceedings of the 14th International Conference on Field Programmable Logic and its Applications (FPL2004), 2004. »»
    Abstract

    conference paper / id: 2288742

    Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures

    Griese, Björn; Vonnahme, Erik; Porrmann, Mario; Rückert, Ulrich

    Dynamic reconfiguration of digital hardware enables systems to adapt to changing demands of the applications and of the environment. This paper concentrates on a core element of a reconfigurable hardware architecture, which supports a Real-time Operating System in reconfiguring the hardware – the Run-time Reconfiguration (RTR) Manager. The RTR-Manager has been developed to control, monitor and execute dynamic reconfiguration. It enables a fast adaptation of the SoC architecture through context switching between different configurations. Configuration code analysis and observation of the reconfiguration process guarantee a correct reconfiguration and increase the safety of the system. The system was successfully implemented and evaluated by means of the Rapid Prototyping System RAPTOR2000.


    In: Proceedings of the 14th International Conference on Field Programmable Logic and its Applications (FPL2004), 2004.
  • Iske, Burkhard; Jäger, Björn; Rückert, Ulrich:
    A Ray-Tracing Approach for Simulating Recognition Abilities of Active Infrared Sensor Arrays.
    In: IEEE Sensors Journal, Volume: 4, 2004. »»
    Abstract

    article / id: 2145314

    A Ray-Tracing Approach for Simulating Recognition Abilities of Active Infrared Sensor Arrays

    Iske, Burkhard; Jäger, Björn; Rückert, Ulrich

    This paper deals with the simulation and evaluation of the recognition abilities of active infrared sensor arrays for autonomous systems. The simulation is based on a Monte Carlo algorithm, which uses ray-tracing to calculate the impulse response of a receiving element. The emphasis lies in an efficient computation, which means that the rays sent should ideally contribute maximally to the final result and that different sender and receiver characteristics should easily be calculable. Extensive experiments were carried out with the simulation mostly taking less than a minute on an Athlon 650 MHz computer and simulated values being a good approximation of the measured values.


    In: IEEE Sensors Journal, Volume: 4, 2004.
  • Grunewald, M.; Niemann, J.-C.; Porrmann, Mario; Rückert, Ulrich:
    A mapping strategy for resource-efficient network processing on multiprocessor SoCs.
    In: Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, Volume: 2, 2004. »»
    Abstract

    conference paper / id: 2286101

    A mapping strategy for resource-efficient network processing on multiprocessor SoCs

    Grunewald, M.; Niemann, J.-C.; Porrmann, Mario; Rückert, Ulrich

    Hardware architectures based on a field of hardwareextended processors can provide flexible computing power for applications where parallelism can be exploited. For multiprocessors, the assignment of functionality to execution units can have a great impact on the performance. Additionally, finding the optimal mapping can be a timeconsuming task. We present a multiprocessor architecture along with a suitable design method that includes an automated solution to the mapping problem. Our hardware architecture employs a network-on-chip (NoC) to achieve a high degree of scalability for the application and for the system in respect to future integration technologies.We also show how to reduce the packet buffer requirements with a proper scheduling strategy and present first estimates for the resource consumption of an application targeted for mobile networking.


    In: Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, Volume: 2, 2004.
  • Kalte, H.; Lee, G.; Porrmann, Mario; Rückert, Ulrich:
    Study on column wise design compaction for reconfigurable systems.
    In: Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, 2004. »»
    Abstract

    conference paper / id: 2286233

    Study on column wise design compaction for reconfigurable systems

    Kalte, H.; Lee, G.; Porrmann, Mario; Rückert, Ulrich

    Some of currently available Field Programmable Care Arrays (FPGAsl can be reconfigured pnrriallv, which makes it possible to build up dynamic systems rhar can be adapred 10 changing demnnds during runtime. One basic aspect of such a system is the wag rhe dynamic hardware modules are placed on the FPGA. As most FPGAs offer parrial reconfigurarion in a column wise manner, a ID placement of column wise implemenred modules seems to be promising. Within this paper we present a design study rhar determines the effects of a column wise module implementarion on the resulring frequency and power consumption'.


    In: Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, 2004.
  • Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
    Leistungsbewertung unterschiedlicher Einbettungsvarianten dynamisch rekonfigurierbarer Hardware.
    In: ARCS 2004 – Organic and Pervasive Computing, 2004. »»
    Abstract

    conference paper / id: 2288708

    Leistungsbewertung unterschiedlicher Einbettungsvarianten dynamisch rekonfigurierbarer Hardware

    Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich

    Die Leistungsfähigkeit eingebetteter dynamisch rekonfigurierbarer Hardware ist von der internen Struktur der rekonfigurierbaren Logik sowie insbesondere von der notwendigen Anbindung an eine Prozessorumgebung abhängig. Ziel dieses Beitrags ist es, die Auswirkungen der Kopplung zwischen Prozessor und Hardware-Erweiterung auf die Leistungsfähigkeit des Gesamtsystems zu analysieren. Hierzu wird die Kommunikation für verschiedene Einbettungsvarianten detailliert modelliert. Anhand eines konkreten Implementierungsbeispiels wird das Modell verifiziert und für eine quantitative Analyse der Einbettung unterschiedlich komplexer Hardware-Erweiterungen in eine Prozessorumgebung genutzt.


    In: ARCS 2004 – Organic and Pervasive Computing, 2004.
  • Vonnahme, Erik; Griese, Björn; Porrmann, Mario; Rückert, Ulrich:
    Dynamische Rekonfiguration echtzeitfähiger Netzwerkschnittstellen.
    In: VDE Kongress 2004 – ITG Fachtagung 'Ambient Intelligence', VDE Verlag, 2004. »»
    Abstract

    conference paper / id: 2288760

    Dynamische Rekonfiguration echtzeitfähiger Netzwerkschnittstellen

    Vonnahme, Erik; Griese, Björn; Porrmann, Mario; Rückert, Ulrich

    Rekonfigurierbare Verarbeitungseinheiten werden in der Regel zur Unterstützung anwendungsspezifischer Aufgaben eingesetzt. Bei dynamischer Rekonfiguration kann dies sogar während der Laufzeit geschehen. In diesem Beitrag soll die Ausweitung des Einsatzgebietes dynamisch rekonfigurierbarer Logik auf Netzwerkschnittstellen betrachtet werden. Die Möglichkeiten, der Nutzen und die Auswirkungen auf die Implementierung dynamisch rekonfigurierbarer Netzwerkschnittstellen werden dargestellt. Von besonderem Interesse sind die Aufrechterhaltung der Verbindung, das Vermeiden von Paketverlusten und die Sicherstellung des Echtzeitbetriebs während der Rekonfiguration. Darüber hinaus werden Methoden für die dynamische Rekonfiguration von Netzwerkschnittstellen und die aktuelle prototypische Implementierung gezeigt.


    In: VDE Kongress 2004 – ITG Fachtagung 'Ambient Intelligence', VDE Verlag, 2004.
  • Minchev, Z.; Manolov, Ognyan; Noykov, Sv.; Witkowski, Ulf; Rückert, Ulrich:
    Fuzzy Logic Based Intelligent Motion Control of Robots Swarm Simulated by Khepera Robots.
    In: IEEE International Conference on Intelligent Systems, 2004. »»
    Abstract

    conference paper / id: 2288796

    Fuzzy Logic Based Intelligent Motion Control of Robots Swarm Simulated by Khepera Robots

    Minchev, Z.; Manolov, Ognyan; Noykov, Sv.; Witkowski, Ulf; Rückert, Ulrich

    The coordination of intelligent behavior among the swarm of autonomous agents and the contrivance of intcrrelntions between the collections are the sine quo non of the Multi-agent Systems (MAS). The .metamorphic robotic systems are a new and rather perspective sphere of robotics because of the different and useful applications. These selfreconliguring robotic systems could be described BS MAS. The metamorphic robots could he considered as B collection’of identical modules and each unit has the ahility to connect, disconnect, climb over its near neighbors or to move independently. The leading scope of this issue is the implementation of Intuitionistic Fuzzy Sets (IFS) in MAS for synthesis of useful technique for optimization. The technique is applied in the strategy for investigation of unknown environment with swarm of Khepera robots.


    In: IEEE International Conference on Intelligent Systems, 2004.
  • Hagen, Gunnar; Niemann, Jörg-Christian; Porrmann, Mario; Sauer, Christian; Slowik, Adrian; Thies, Michael:
    Developing an IP-DSLAM Benchmark for Network Processor Units.
    In: ANCHOR 2004, Advanced Networking and Communications Hardware Workshop, held in conjunction with the 31st Annual International Symposium on Computer Architecture (ISCA 2004), 2004. »»

    conference paper / id: 2494463

  • Vonnahme, E.; Griese, G.; Porrmann, Mario; Rückert, Ulrich:
    Dynamic Reconfiguration of Real-Time Network Interfaces.
    In: Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, 2004. »»
    Abstract

    conference paper / id: 2285912

    Dynamic Reconfiguration of Real-Time Network Interfaces

    Vonnahme, E.; Griese, G.; Porrmann, Mario; Rückert, Ulrich

    The programmable resources of reconfigurable computing architectures are commonly used to support application specific processing. Dynamic reconfiguration enables hardware adaptation even during run-time. This paper concentrates on extending the application of dynamically reconfigurable logic to the area of network interface logic. The benefits and consequences of implementing even low-level networking functions in programmable hardware over fixed realizations are explained, and the possibilities arising from reconfigurable network interfaces are shown. Concerning reconfiguration of the network interface subsystem at run-time, maintaining connections, preventing packet loss, and guaranteeing response times during reconfiguration is crucial. Methods for dynamically replacing network interface hardware are described, and the current prototype is shown.


    In: Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, 2004.
  • Witkowski, U.; Rückert, Ulrich:
    Pattern synchronization for associative memory in pulse coded neural networks.
    In: Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on, Volume: 2, 2004. »»
    Abstract

    conference paper / id: 2285962

    Pattern synchronization for associative memory in pulse coded neural networks

    Witkowski, U.; Rückert, Ulrich

    For image processing a lot of algorithms have been developed in the past that are well suited for specific tasks. These algorithms are often optimized for high performance computers with high power consumption, thus, it is not possible to use these algorithms for mobile applications. In this paper, a massive parallel vision system is partly discussed which is biologically inspired and requires less power. This system consists of several layers of pulsed neural networks, e.g. some layers form specific features detectors to decompose the input image in several features. The features are completed or bound by an associative memory that needs a synchronized input pulse pattern. In this paper, we focus on the synchronization stage of the system that is combined with the associative memory. The discussed synchronization unit detects correlated pulses in the network, collects them and activates a synchrones output pattern.


    In: Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on, Volume: 2, 2004.
  • Beiu, V.; Rückert, Ulrich; Roy, S.; Nyathi, J.:
    On nanoelectronic architectural challenges and solutions.
    In: Nanotechnology, 2004. 4th IEEE Conference on, 2004. »»
    Abstract

    conference paper / id: 2286376

    On nanoelectronic architectural challenges and solutions

    Beiu, V.; Rückert, Ulrich; Roy, S.; Nyathi, J.

    This paper discusses the many challenges in the design of future nano architectures that result from the use of nanoelectronic devices. The relations among these challenges are studied, and an unfortunately subjective relative ranking is proposed. Possible solutions are suggested.


    In: Nanotechnology, 2004. 4th IEEE Conference on, 2004.
  • Brinkmann, André; Heidebuer, Michael; Meyer auf der Heide, Friedhelm; Rückert, Ulrich; Salzwedel, Kay; Vodisek, Mario:
    V:Drive – Costs and Benefits of an Out-of-Band Storage Virtualization System.
    In: Proceedings of the 12th NASA Goddard, 21st IEEE Conference on Mass Storage Systems and Technologies (MSST), 2004. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2288714

    V:Drive – Costs and Benefits of an Out-of-Band Storage Virtualization System

    Brinkmann, André; Heidebuer, Michael; Meyer auf der Heide, Friedhelm; Rückert, Ulrich; Salzwedel, Kay; Vodisek, Mario

    The advances in network technology and the growth of the Internet together with upcoming new applications like peer-to-peer (P2P) networks have led to an exponential growth of the stored data volume. The key to manage this data explosion seems to be the consolidation of storage systems inside storage area networks (SANs) and the use of a storage virtualization solution that is able to abstract from the underlying physical storage system. In this paper we present the first measurements on an out-of-band storage virtualization system and investigate its performance and scalability compared to a plain SAN. We show in general that a carefully designed out-of-band solution has only a very minor impact on the CPU usage in the connected servers and that the metadata management can be efficiently handled. Furthermore we show that the use of an adaptive data placement scheme in our virtualization solution V:Drive can significantly enhance the throughput of the storage systems, especially in environments with random access schemes.


    In: Proceedings of the 12th NASA Goddard, 21st IEEE Conference on Mass Storage Systems and Technologies (MSST), 2004.
  • Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich:
    Parallele Architekturen für Netzwerkprozessoren.
    In: Ambient Intelligence, VDE Kongress, Volume: 1, VDE Verlag, 2004. »»
    Fulltext (external) Abstract

    conference paper / id: 2288776

    Parallele Architekturen für Netzwerkprozessoren

    Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich

    Informationsverarbeitung und Vernetzung von technischen Geräten halten mehr und mehr Einzug in unser tägli-ches Leben. Um das dabei ständig wachsende Datenaufkommen zu verarbeiten, bedarf es leistungsfähiger Kno-tenpunkte in Sprach- und Datennetzwerken. In diesem Artikel stellen wir eine Architektur für Netzwerkprozes-soren vor, die auf einer homogenen, massiv parallelen Struktur basiert. Sie ist für unterschiedliche Einsatzgebiete skalierbar und durch spezielle Hardwarebeschleuniger für die Zielapplikation optimierbar, um besonders res-sourceneffizient zu sein. Wir zeigen Anforderungen für zwei Netzwerk-Anwendungsszenarien auf und stellen die Leistungssteigerung durch die von uns implementierten Hardware-Erweiterungen dar.


    In: Ambient Intelligence, VDE Kongress, Volume: 1, VDE Verlag, 2004.
  • Chinapirom, Teerapat; Kaulmann, Tim; Witkowski, Ulf; Rückert, Ulrich:
    Visual Object Recognition by 2D-Color Camera and On-Board Information Processing for Minirobots.
    In: Proceedings of the FIRA Robot World Congress, 2004. »»

    conference paper / id: 2288788

  • Franzmeier, M.; Pohl, C.; Porrmann, Mario; Rückert, Ulrich:
    Hardware Accelerated Data Analysis.
    In: Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, 2004. »»
    Abstract

    conference paper / id: 2285942

    Hardware Accelerated Data Analysis

    Franzmeier, M.; Pohl, C.; Porrmann, Mario; Rückert, Ulrich

    In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times. Our system consists of Processing Elements (PEs) working completely in parallel on the task of SOM simulation. We will show the scalability of the system concerning precision and number of PEs, as well as the flexibility of the system regarding size and shape of the simulated maps. The possibility of emulating virtual maps (one PE emulates more than one neuron) enables the computation of maps with more neurons than PEs. Benchmarking results of our FPGA (Field Programmable Gate Array) based implementation of the system show the high performance of our accelerator.


    In: Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, 2004.
  • Kalte, H.; Porrmann, Mario; Rückert, Ulrich:
    System-on-programmable-chip approach enabling online fine-grained 1D-placement.
    In: Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International, 2004. »»
    Abstract

    conference paper / id: 2286356

    System-on-programmable-chip approach enabling online fine-grained 1D-placement

    Kalte, H.; Porrmann, Mario; Rückert, Ulrich

    The increasing logic density of current FPGAs (Field Programmable Gate Arrays) enables the integration of whole systems on one programmable chip. Some of these FPGAs provide the additional feature of partial dynamic reconfiguration, which permits to change parts of the device while other parts keep working. Combining the features of system level density and partial dynamic reconfiguration enables the integration of dynamic systems that can be adopted to changing demands during runtime. A lot of theoretical work in this challenging research area has been done on efficiently placing and scheduling modules on the FPGA area. However, there is a lack of applied approaches that can be realized by existing tools and FPGAs. In this paper we present a new, realizable approach for the dynamic system integration on Xilinx Virtex FPGAs. In contrast to the existing approaches that consider fixed slots for the module placement, our approach enables the fine-grained placement of modules with variable width along a horizontal communication infrastructure.


    In: Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International, 2004.
  • Grünewald, Matthias; Xu, Feng; Rückert, Ulrich:
    Power Control in Directional Mobile Ad Hoc Networks.
    In: VDE Kongress – ITG Fachtagung 'Ambient Intelligence', 2004. »»

    conference paper / id: 2288768

  • Witkowski, Ulf; Rückert, Ulrich:
    Aktives Nachtsichtsystem für autonome mobile Roboter.
    In: VDE Kongress 2004 – ITG Fachtagung 'Ambient Intelligence'., Volume: 1, 2004. »»

    conference paper / id: 2288782

  • Grunewald, M.; Le, D.K.; Kastens, U.; Niemann, J.-C.; Porrmann, Mario; Rückert, Ulrich; Slowik, A.; Thies, M.:
    Network application driven instruction set extensions for embedded processing clusters.
    In: Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, 2004. »»
    Abstract

    conference paper / id: 2286146

    Network application driven instruction set extensions for embedded processing clusters

    Grunewald, M.; Le, D.K.; Kastens, U.; Niemann, J.-C.; Porrmann, Mario; Rückert, Ulrich; Slowik, A.; Thies, M.

    This paper addresses the design automation of instruction set extensions for application-specific processors with emphasis on network processing. Within this domain, increasing performance demands and the ongoing development of network protocols both call for flexible and performance-optimized processors. Our approach represents a holistic methodology for the extension and optimization of a processorýs instruction set. The starting point is a concise yet powerful processor abstraction, which is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator so that domain-characteristic benchmarks can be analyzed for frequently occurring instruction pairs. These instruction pairs are promising candidates for the extension of the instruction set by means of super-instructions. Provided that a new super-instruction meets a given performance threshold, a fine-grained performance re-evaluation of the adapted processor design can be conducted instantly. With respect to the chosen domain-characteristic benchmark, the tool-chain pinpoints important characteristics such as execution performance, energy consumption, or chip area of the extended design. Using this holistic design methodology, we are able to judge a refinement of the processor rapidly.


    In: Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, 2004.
  • Grünewald, Matthias; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich:
    A framework for design space exploration of resource efficient network processing on multiprocessor SoCs.
    In: Proceedings of the 3rd Workshop on Network Processors & Applications, 2004. »»
    Abstract

    conference paper / id: 2288700

    A framework for design space exploration of resource efficient network processing on multiprocessor SoCs

    Grünewald, Matthias; Niemann, Jörg-Christian; Porrmann, Mario; Rückert, Ulrich

    Hardware architectures based on a field of hardwareextended processors can provide flexible computing power for applications where parallelism can be exploited. For multiprocessors, the assignment of functionality to execution units can have a great impact on the performance. Additionally, finding the optimal mapping can be a timeconsuming task. We present a multiprocessor architecture along with a suitable design method that includes an automated solution to the mapping problem. Our hardware architecture employs a network-on-chip (NoC) to achieve a high degree of scalability for the application and for the system in respect to future integration technologies.We also show how to reduce the packet buffer requirements with a proper scheduling strategy and present first estimates for the resource consumption of an application targeted for mobile networking.


    In: Proceedings of the 3rd Workshop on Network Processors & Applications, 2004.
  • Witkowski, Ulf; Chinapirom, Teerapat; Du, Jia Lei; Rückert, Ulrich; Manolov, Ognyan:
    Cooperating autonomous and mobile minirobots in dynamic environments.
    In: International Federation of Automatic Control – IFAC – DECOM-TT, 2004. »»

    conference paper / id: 2288750

2003
  • Rückert, Ulrich:
    Mediatronics – Things That Communicate And Cooperate.
    In: Proceedings of the International Conference Automatics and Informatics’03, Volume: 1, 2003. »»

    conference paper / id: 2288665

  • Grunewald, M.; Niemann, J.-C.; Rückert, Ulrich:
    A performance evaluation method for optimizing embedded applications.
    In: System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on, 2003. »»
    Abstract

    conference paper / id: 2285956

    A performance evaluation method for optimizing embedded applications

    Grunewald, M.; Niemann, J.-C.; Rückert, Ulrich

    Performance evaluation is an important step for designing embedded applications that require small footprints, low energy consumption and high throughput. We present a simulation-based method to characterize several resource properties (memory accesses, energy consumption, execution time) of embedded software that runs on dedicated processing engines targeted for SoC designs. The results of the characterization process are back-annotated to the source code to aid the designer in optimizing the implementation. Our approach allows the replacement of software parts by hardware units to speed up processing. We have performed case studies with software and hardware implementations of a pseudo-random number generator and a transmission error detector. The results show that computation speed-ups and energy reductions up to a factor of 15 can be obtained with implementations that exploit hardware extensions.


    In: System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on, 2003.
  • Bonorden, O.; Bruls, N.; Kastens, U.; Le, Dinh Khoi; Heide auf der, F.M.; Niemann, J.-C.; Porrmann, Mario; Rückert, Ulrich; Slowik, A.; Thies, M.:
    A holistic methodology for network processor design.
    In: Local Computer Networks, 2003. LCN '03. Proceedings. 28th Annual IEEE International Conference on, 2003. »»
    Abstract

    conference paper / id: 2286024

    A holistic methodology for network processor design

    Bonorden, O.; Bruls, N.; Kastens, U.; Le, Dinh Khoi; Heide auf der, F.M.; Niemann, J.-C.; Porrmann, Mario; Rückert, Ulrich; Slowik, A.; Thies, M.

    The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, evaluation, and realization of a parameterizable network processing unit. In this paper we present a design methodology for network processors which encompasses the research areas from the application software down to the gate level of the chip. Key components of this holistic approach have been successfully applied to characteristic examples of architecture refinements.


    In: Local Computer Networks, 2003. LCN '03. Proceedings. 28th Annual IEEE International Conference on, 2003.
  • Grünewald, Matthias; Rückert, Ulrich:
    A Khepera communication module supporting directed power-variable transmission.
    In: Proceedings of the 2nd International Conference on Autonomous Minirobots for Research and Edutainment, 2003. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2288645

    A Khepera communication module supporting directed power-variable transmission

    Grünewald, Matthias; Rückert, Ulrich

    We present a prototype of an infrared communication module for the mini robot Khepera. Compared to other wireless communication modules, it features bi-directional transmission in eight sectors (directions) with variable transmission power. The maximum communication distance is unit[1]m at a data rate of unit[23.4]kbps. Our demonstration shows two Kheperas that establish a communication link. The transmission power can be adjusted and the received signal strength as well as the direction-of-arrival (DOA) of theincoming signal are shown.


    In: Proceedings of the 2nd International Conference on Autonomous Minirobots for Research and Edutainment, 2003.
  • Rückert, Ulrich; Sitte, Joaquin; Witkowski, Ulf:
    Autonomous Minirobots for Research and Edutainment.
    In: AMIRE Int. Conf., 2003. »»

    conference publication / id: 2285753

  • Klahold, Jürgen; Jürgens, Hartmut; Rückert, Ulrich:
    Neural Object Classification Using Ultrasonic Spectrum Analysis.
    In: Proceedings of the 2nd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), 2003. »»
    Abstract

    conference paper / id: 2288625

    Neural Object Classification Using Ultrasonic Spectrum Analysis

    Klahold, Jürgen; Jürgens, Hartmut; Rückert, Ulrich

    This paper describes how reflected broadband sound signals are marked by interference phenomena if the surface of the ensonified object is structured. For an efficient extraction of features of the signal that relate to the surface structure of the object, the calculation of the cepstrum is introduced. A cylindrical test object is presented, which shows an angle independent and an angle dependent structure. This allows to specify the accuracy of the discrimination of structure sizes, that is based on a selected part of the cepstrum. In addition, the object can be used as a landmark for ultrasonic sensing. Classification of the cepstra is done by the statistical ‘One Nearest Neighbour’ (1NN) method as well as by a ‘Kohonen Self-Organising Feature Map’ (SOM). The results show, that changes in structure size down to 0.1mm are detectable.


    In: Proceedings of the 2nd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE), 2003.
  • Grünewald, Matthias; Rückert, Ulrich; Schindelhauer, Christian; Volbert, Klaus:
    Directed power-variable infrared communication for the mini robot Khepera.
    In: Proceedings of the 2nd International Conference on Autonomous Minirobots for Research and Edutainment, 2003. »»
    Abstract

    conference paper / id: 2288637

    Directed power-variable infrared communication for the mini robot Khepera

    Grünewald, Matthias; Rückert, Ulrich; Schindelhauer, Christian; Volbert, Klaus

    Communication facilities are important in Robotics if several robots have to work together. In this paper, we describe problems and solutions encountered while de- signing an infrared-based communication device for the mini robot Khepera. In contrast to traditional omnidirectional systems, it features directed, power-variable transmission in eight directions at 23.4 kbps up to a range of 1m . It can differentiate incoming data sig- nals from interference from adjacent sectors and can estimate their direction-of-arrival. We model the transmission over the infrared channel and show how interference influences the reception of the data signals. We also describe methods how to reduce these effects. We have tested the performance of the resulted signal processing in a worst case scenario by simulations and in experiments with a prototype implementation. The resulted module is especially suited for experimental evaluation of ad hoc network protocols and for position estimation.


    In: Proceedings of the 2nd International Conference on Autonomous Minirobots for Research and Edutainment, 2003.
  • Brinkmann, André; Meyer auf der Heide, Friedhelm; Salzwedel, Kay; Scheideler, Christian; Vodisek, Mario; Rückert, Ulrich:
    Storage Management as Means to cope with Exponential Information Growth.
    In: Proceedings of SSGRR 2003, 2003. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2288649

    Storage Management as Means to cope with Exponential Information Growth

    Brinkmann, André; Meyer auf der Heide, Friedhelm; Salzwedel, Kay; Scheideler, Christian; Vodisek, Mario; Rückert, Ulrich

    The advances in Internet technology have led to tremendous improvements in business, education, and science and have changed the way we think, live, and communicate. Information exchange has become ubiquitous by the possibilities offered through modern technologies. We are able to offer information 24 hours a day through our web sites and can leave messages every time and from anywhere in the world. This change in communication has led to new challenges. Enterprises have to deal with an information amount that doubles every year. The technological foundation to cope with this information explosion is given by Storage Area Networks (SANs), which are able to connect a great number of storage systems over a fast interconnection network. However, to be able to use the benefits of a SAN, an easy-to-use and efficient management support has to be given to the storage administrator. In this paper, we will suggest new storage management concepts and we will introduce a new management environment that is able to significantly reduce management costs and increases the performance and resource utilization of the given SAN infrastructure.


    In: Proceedings of SSGRR 2003, 2003.
  • Witkowski, Ulf; Rückert, Ulrich:
    Positioning System for the Minirobot Khepera based on Self-organizing Feature Maps.
    In: KAIST Press, 2003. »»

    book / id: 2285644

  • Witkowski, Ulf; Bandyk, Mariusz; Rückert, Ulrich:
    Long-running Experiments using the Minirobot Khepera with Automatic Charging Station.
    In: Proc. of the 2nd International Conference on Autonomous Minirobots for Research and Edutainment AMiRE03, 2003. »»
    Abstract

    conference paper / id: 2288617

    Long-running Experiments using the Minirobot Khepera with Automatic Charging Station

    Witkowski, Ulf; Bandyk, Mariusz; Rückert, Ulrich

    Ultrasonic sensors enable mobile autonomous systems to obtain information about obstacles in large environments. In the presented work, taking the limited energy resources of a mobile robot into account, only one transmitter is used. The employment of two receivers permits the calculation of the distance and direction of objects. Using pseudo-random sequences, simultaneously transmitting and receiving with the continuous perception of the environment is possible. The sequences are modulated in order to op- timise the signal-to-noise ratio and energy consumption with respect to the transducers’ bandwidth. With the gained signals the echo-intensity £eld is calculated for object detec- tion. Furthermore, several robots could operate in the same region applying orthogonal sequences.


    In: Proc. of the 2nd International Conference on Autonomous Minirobots for Research and Edutainment AMiRE03, 2003.
  • Iske, Burkhard; Schlößer, Stefan; Rückert, Ulrich:
    Resolution Analysis of Infrared Sensor Arrays.
    In: Proceedings of the 2nd International Conference on Autonomous Minirobots for Research and Edutainment (AMiRE), 2003. »»
    Abstract

    conference paper / id: 2288631

    Resolution Analysis of Infrared Sensor Arrays

    Iske, Burkhard; Schlößer, Stefan; Rückert, Ulrich

    This work deals with simple and low-cost IR-sensor systems for autonomous systems. Specifically, a circular array of IR-photodiodes is investigated in the context of object recognition, localisation and differentiation. Such sensors are usually only used for the detection of objects in the near field of the system in order to avoid obstacles. However, under certain conditions, the information provided by circular IR-sensor arrays can be used to determine the angle, distance and brightness of an object. Besides a theoretical analysis of the minimal requirements for determining the number of objects and their parameters, noisy sensor readings are investigated concerning maximum possible preciseness of the estimation of the object’s distance. Finally, an algorithm that allows the determination of the distance and angle of an object, independent of knowledge of its brightness, is presented.


    In: Proceedings of the 2nd International Conference on Autonomous Minirobots for Research and Edutainment (AMiRE), 2003.
  • Grünewald, Matthias; Iske, Burkhard; Klahold, Jürgen; Manolov, Ognyan; Orhan, Orhan; Rückert, Ulrich; Witkowski, Ulf:
    Communication Between Khepera Mini Robots For Cooperative Positioning.
    In: Proceedings of the International Conference Automatics and Informatics’03, Volume: 1, 2003. »»
    Fulltext (PDF)

    conference paper / id: 2288667

  • Manolov, Ognyan; Iske, Burkhard; Noykov, Sv.; Klahold, Jürgen; Georgiev, G.; Witkowski, Ulf; Rückert, Ulrich:
    Gard – An Intelligent System for Distributed Exploration of Landmine Fields Simulated by a Team of Khepera Robots.
    In: Proceedings of the International Conference Automatics and Informatics’03, Volume: 1, 2003. »»
    Fulltext (PDF)

    conference paper / id: 2288681

  • Porrmann, Mario; Witkowski, Ulf; Rückert, Ulrich:
    A Massively Parallel Architecture for Self-Organizing Feature Maps.
    In: IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, Volume: 14, 2003. »»
    Abstract

    article / id: 2145324

    A Massively Parallel Architecture for Self-Organizing Feature Maps

    Porrmann, Mario; Witkowski, Ulf; Rückert, Ulrich

    A hardware accelerator for self-organizing feature maps is presented. We have developed a massively parallel architecture that, on the one hand, allows a resource-efficient implementation of small or medium-sized maps for embedded applications, requiring only small areas of silicon. On the other hand, large maps can be simulated with systems that consist of several integrated circuits that work in parallel. Apart from the learning and recall of self-organizing feature maps, the hardware accelerates data pre- and postprocessing. For the verification of our architectural concepts in a real-world environment, we have implemented an ASIC that is integrated into our heterogeneous multiprocessor system for neural applications. The performance of our system is analyzed for various simulation parameters. Additionally, the performance that can be achieved with future microelectronic technologies is estimated.


    In: IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, Volume: 14, 2003.
  • Witkowski, Ulf; Rückert, Ulrich:
    Development and Incorporation of Elementary Soccer Strategies for the Khepera Mini Robot.
    In: Proc. of the FIRA Robot World Congress 2003, 2003. »»

    conference paper / id: 2288661

2002
  • Porrmann, Mario; Franzmeier, M.; Kalte, H.; Witkowski, U.; Rückert, Ulrich:
    A Reconfigurable SOM Hardware Accelerator.
    In: 10th European Symposium on Artificial Neural Networks, 2002. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2288603

    A Reconfigurable SOM Hardware Accelerator

    Porrmann, Mario; Franzmeier, M.; Kalte, H.; Witkowski, U.; Rückert, Ulrich

    A dynamically reconfigurable hardware accelerator for self-organizing feature maps is presented. The system is based on the universal rapid prototyping system RAPTOR2000 that has been developed by the authors. The modular prototyping system is based on XILINX FPGAs and is capable of emulating hardware implementations with a complexity of more than 24 million system gates. RAPTOR2000 is linked to its host – a standard personal computer or workstation – via the PCI bus. For the simulation of self-organizing maps a module has been designed for the RAPTOR2000 system, that embodies an FPGA of the Xilinx Virtex series and optionally up to 128 MBytes of SDRAM. A speedup of about 50 is achieved with five FPGA modules on the RAPTOR2000 system compared to a software implementation on a state of the art personal computer for typical applications of self-organizing maps.


    In: 10th European Symposium on Artificial Neural Networks, 2002.
  • Porrmann, Mario:
    Leistungsbewertung eingebetteter Neurocomputersysteme. Dissertation..
    In: Volume: 104, HNI-Verlagsschriftenreihe, Heinz Nixdorf Institut, Schaltungstechnik, 2002. »»

    book / id: 2493620

  • Heittmann, Arne; Rückert, Ulrich:
    Mixed Mode VLSI Implementation of a Neural Associative Memory.
    In: Analog Integrated Circuits and Signal Processing, Volume: 30, 2002. »»
    Abstract

    article / id: 2145340

    Mixed Mode VLSI Implementation of a Neural Associative Memory

    Heittmann, Arne; Rückert, Ulrich

    A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a n×m matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. Although analog circuits suffer from device mismatch a moderate precision of the circuit is acceptable since for the given associative memory model only few parts of the circuit participate on the performed information processing steps. Thus, the information processing elements can be integrated very densely on one chip and hence large scale integration with a large number of connection weights is feasible


    In: Analog Integrated Circuits and Signal Processing, Volume: 30, 2002.
  • Iske, B.; Jager, B.; Rückert, Ulrich:
    A ray-tracing approach for simulating recognition abilities of active infrared sensor arrays.
    In: Sensors, 2002. Proceedings of IEEE, Volume: 2, 2002. »»
    Abstract

    conference paper / id: 2286093

    A ray-tracing approach for simulating recognition abilities of active infrared sensor arrays

    Iske, B.; Jager, B.; Rückert, Ulrich

    The construction and setup of sensors or sensor arrays determines their maximum resolution and recognition abilities. Therefore, the analysis of certain setups is an important and mandatory task during the design process of a new sensor system. This paper deals with the simulation and evaluation of the recognition abilities of active infrared sensors for autonomous systems. Additionally, the simulation method as well as the results provide useful information for other applications, where infrared sensors are used. The simulation method is based on a Monte Carlo algorithm, which uses ray tracing to calculate the impulse response of the optical channel consisting of the sending and receiving components and the environment. In order to allow a fast simulation of several configurations, an efficient and flexible computation is realized. This means that all rays contribute maximally to the final result, and different sensor characteristics can easily be calculated. Extensive experiments are carried out, and the results show different evaluation options.


    In: Sensors, 2002. Proceedings of IEEE, Volume: 2, 2002.
  • Kalte, H.; Langen, D.; Vonnahme, E.; Brinkmann, A.; Rückert, Ulrich:
    Dynamically reconfigurable system-on-programmable-chip.
    In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, 2002. »»
    Abstract

    conference paper / id: 2286322

    Dynamically reconfigurable system-on-programmable-chip

    Kalte, H.; Langen, D.; Vonnahme, E.; Brinkmann, A.; Rückert, Ulrich

    Today’s high-density FPGAs and intellectual property (IP) components enable the integration of complex systems in one programmable chip. New design strategies and concepts have to be developed in order to utilize the new system-level integration facilities. The approach introduced within this paper describes the implementation of a communication infrastructure that provides a number of on-chip IP-sockets. By using the FPGA-feature of partial dynamic reconfiguration, different IP components can be plugged into these sockets during runtime. This leads to a reconfigurable system that can be adapted to varying demands. In this context we designed a 32-bit RISC processor and an AMBA on-chip interconnection bus. Finally we mapped these components on a reconfigurable systemlevel FPGA. The resulting sizes and the utilization of the FPGA’s resources are presented within the last part of this paper.


    In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, 2002.
  • Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
    A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs.
    In: Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), 2002. »»

    conference paper / id: 2288575

  • Klahold, J.; Rautenberg, J.; Rückert, Ulrich:
    Continuous sonar sensing for mobile mini-robots.
    In: Robotics and Automation, 2002. Proceedings. ICRA '02. IEEE International Conference on, Volume: 1, 2002. »»
    Abstract

    conference paper / id: 2286112

    Continuous sonar sensing for mobile mini-robots

    Klahold, J.; Rautenberg, J.; Rückert, Ulrich

    Ultrasonic sensors enable mobile autonomous systems to obtain information about obstacles in large environments. In the presented work, a 5cm broad array of three piezo-ceramic ultrasonic transducers is employed for getting two-dimensional impressions of the surroundings. Deviating from the pulse echo measurement techniques used so far the time-continuous transmitting and receiving from modulated pseudo-random sequences are regarded. Thus the narrow bandwidth of a piezo-ceramic transducer can be compensated by an increased measuring period. An advanced analysis of the correlated signals allows the rejection of phantoms caused by multiple reflections. Furthermore, a classification of objects as wall, corner, log or, cylinder is possible.


    In: Robotics and Automation, 2002. Proceedings. ICRA '02. IEEE International Conference on, Volume: 1, 2002.
  • Rückert, Ulrich; Schmidt, Marco:
    Neural Associative Memory For Content-Based Information Retrieval.
    In: Proceedings of the First International Conference on Intelligent Computing and Information Systems, ICICIS, 2002. »»

    conference paper / id: 2288581

  • Rückert, Ulrich:
    ULSI Architectures for Artificial Neural Networks.
    In: IEEE Micro, Volume: 22, 2002. »»
    Abstract

    article / id: 2285618

    ULSI Architectures for Artificial Neural Networks

    Rückert, Ulrich

    No clear consensus exists about how to exploit the potential for massively parallel implementations of artificial neural networks. Three hardware implementations to demonstrate the key issues surrounding their use are: model specific integrated circuits for neural associative memories, self-organizing feature maps, and local cluster neural networks


    In: IEEE Micro, Volume: 22, 2002.
  • Schäfer, Martin; Schönauer, Tim; Wolff, Carsten; Hartmann, Georg; Klar, H.; Rückert, Ulrich:
    Simulation of Spiking Neural Networks – Architectures and Implementations.
    In: Neurocomputing, Volume: 48, 2002. »»
    Fulltext (PDF) Abstract

    article / id: 2285620

    Simulation of Spiking Neural Networks – Architectures and Implementations

    Schäfer, Martin; Schönauer, Tim; Wolff, Carsten; Hartmann, Georg; Klar, H.; Rückert, Ulrich

    The fast simulation of large networks of spiking neurons is a major task for the ex- amination of biology-inspired vision systems. Networks of this type label features by syn- chronization of spikes and there is strong demand to simulate these e


    In: Neurocomputing, Volume: 48, 2002.
  • Porrmann, Mario; Witkowski, U.; Kalte, H.; Rückert, Ulrich:
    Implementation of artificial neural networks on a reconfigurable hardware accelerator.
    In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, 2002. »»
    Abstract

    conference paper / id: 2285896

    Implementation of artificial neural networks on a reconfigurable hardware accelerator

    Porrmann, Mario; Witkowski, U.; Kalte, H.; Rückert, Ulrich

    The hardware implementation of three different artificial neural networks is presented. The basis for the implementation is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementational issues are considered. Especially resource-efficiency and performance of the presented realizations are discussed.


    In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, 2002.
  • Brinkmann, A.; Niemann, J.-C.; Hehemann, I.; Langen, D.; Porrmann, Mario; Rückert, Ulrich:
    On-chip interconnects for next generation system-on-chips.
    In: ASIC/SOC Conference, 2002. 15th Annual IEEE International, 2002. »»
    Abstract

    conference paper / id: 2285966

    On-chip interconnects for next generation system-on-chips

    Brinkmann, A.; Niemann, J.-C.; Hehemann, I.; Langen, D.; Porrmann, Mario; Rückert, Ulrich

    Today's deep submicron fabrication technologies enable design enginefrs to put an impressive number of eomponfnts like micropmeessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions oftransistors can be integrated on one die and form a parallel system, consisting out of thousands of components. To handle this impressive number of components it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient on-chip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers unto the design of Secs and proposes an on-chip architecture which is based on active switch bores. We will show that this architecture is able lo fill the existing design gap between an efficient use of the design space and the design complexity with reasonable resource requirements.


    In: ASIC/SOC Conference, 2002. 15th Annual IEEE International, 2002.
  • Witkowski, Ulf; Rückert, Ulrich:
    Positioning System for the Minirobot Khepera based on Self-organizing Feature Maps.
    In: Proceedings of 2002 FIRA Robot World Congress, 2002. »»

    conference paper / id: 2288585

  • Iske, Burkhard; Löffler, Axel; Rückert, Ulrich:
    A Direction Sensitive Network Based on a Biophysical Neurone Model.
    In: Artificial Neural Networks- ICANN 2002, Springer-Verlag, 2002. »»
    Abstract

    conference paper / id: 2288597

    A Direction Sensitive Network Based on a Biophysical Neurone Model

    Iske, Burkhard; Löffler, Axel; Rückert, Ulrich

    To our understanding, modelling the dynamics of brain functions on cell level is essential to develop both a deeper understanding and classification of the experimental data as well as a guideline for further research. This paper now presents the implementation and training of a direction sensitive network on the basis of a biophisical neurone model including synaptic excitation, dendritic propagation and action-potential generation. The underlying model not only describes the functional aspects of neural signal processing, but also provides insight into their underlying energy consumption. Moreover, the training data set has been recorded by means of a real robotics system, thus bridging the gap to technical applications.


    In: Artificial Neural Networks- ICANN 2002, Springer-Verlag, 2002.
  • Langen, D.; Rückert, Ulrich:
    Extending scaling theory by adequately considering velocity saturation.
    In: ASIC/SOC Conference, 2002. 15th Annual IEEE International, 2002. »»
    Abstract

    conference paper / id: 2286057

    Extending scaling theory by adequately considering velocity saturation

    Langen, D.; Rückert, Ulrich

    This paper addresses the problem of comparing the performance and the area and power consumption of integrated circuits built in different technologies. In the literature there are several methods described hut these do not sufficiently take the velocity saturation into account. They either ignore velocity saturation or assume the device is always in velocity saturation. The approach presented in this paper handles the effects of velocity saturation more adequately.


    In: ASIC/SOC Conference, 2002. 15th Annual IEEE International, 2002.
  • Langen, Dominik; Niemann, Jörg-Christian; Porrmann, Mario; Kalte, Heiko; Rückert, Ulrich:
    Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation.
    In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), 2002. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2288565

    Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation

    Langen, Dominik; Niemann, Jörg-Christian; Porrmann, Mario; Kalte, Heiko; Rückert, Ulrich

    In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze the differences between a prototypical FPGA implementation and standard cell realizations in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using the hardware description language VHDL, which offers the opportunity of adding special, optimized hardware blocks for various operations. The effects on area and power consumption as well as computational power are analyzed. A detailed overview of the implementation of additional hardware multipliers and their effects on the above mentioned topics concludes this paper.


    In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), 2002.
  • Porrmann, Mario; Witkowski, Ulf; Kalte, Heiko; Rückert, Ulrich:
    Dynamically Reconfigurable Hardware – A New Perspective for Neural Network Implementations.
    In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2002), 2002. »»
    Abstract

    conference paper / id: 2288589

    Dynamically Reconfigurable Hardware – A New Perspective for Neural Network Implementations

    Porrmann, Mario; Witkowski, Ulf; Kalte, Heiko; Rückert, Ulrich

    Today’s high-density FPGAs and intellectual property (IP) components enable the integration of complex systems in one programmable chip. New design strategies and concepts have to be developed in order to utilize the new system-level integration facilities. The approach introduced within this paper describes the implementation of a communication infrastructure that provides a number of on-chip IP-sockets. By using the FPGA-feature of partial dynamic reconfiguration, different IP components can be plugged into these sockets during runtime. This leads to a reconfigurable system that can be adapted to varying demands. In this context we designed a 32-bit RISC processor and an AMBA on-chip interconnection bus. Finally we mapped these components on a reconfigurable systemlevel FPGA. The resulting sizes and the utilization of the FPGA’s resources are presented within the last part of this paper.


    In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL2002), 2002.
2001
  • Rückert, Ulrich; Sitte, Joaquin; Witkowski, Ulf:
    Autonomous Minirobots for Research and Edutainment.
    In: Volume: 97, Heinz Nixdorf Institut, Universität Paderborn, 2001. »»

    conference publication / id: 2285736

  • Iske, B.; Rückert, Ulrich:
    A methodology for behaviour design of autonomous systems.
    In: Intelligent Robots and Systems, 2001. Proceedings. 2001 IEEE/RSJ International Conference on, Volume: 1, 2001. »»
    Abstract

    conference paper / id: 2285818

    A methodology for behaviour design of autonomous systems

    Iske, B.; Rückert, Ulrich

    A new methodology of behaviour design and modelling is proposed, which is based on a tree structure. The tree allows a structured design and overview of autonomous systems behaviours. A behaviour of higher abstraction level consists of a combination of one or several behaviours of lower abstraction level. The advantage of the tree becomes clear when wanting to reuse already developed behaviours. In order to reuse a behaviour of higher level of abstraction several behaviours of lower level of abstraction are required, which can easily be identified when describing a behaviour in the proposed tree structure. Lower levels of behaviour are mostly system dependant. By replacing only the behaviours of low level of abstraction behaviours can easily be transferred to other systems. Additionally, the behaviour tree enables the estimation and evaluation of resource requirements of different behaviours of diflerent levels of abstraction.


    In: Intelligent Robots and Systems, 2001. Proceedings. 2001 IEEE/RSJ International Conference on, Volume: 1, 2001.
  • Rückert, Ulrich:
    ULSI architectures for artificial neural networks.
    In: Parallel and Distributed Processing, 2001. Proceedings. Ninth Euromicro Workshop on, 2001. »»
    Abstract

    conference paper / id: 2285832

    ULSI architectures for artificial neural networks

    Rückert, Ulrich

    No clear consensus exists about how to exploit the potential for massively parallel implementations of artificial neural networks. Three hardware implementations demonstrate key issues surrounding their use.


    In: Parallel and Distributed Processing, 2001. Proceedings. Ninth Euromicro Workshop on, 2001.
  • Schmidt, M.; Rückert, Ulrich:
    Content-based information retrieval using an embedded neural associative memory.
    In: Parallel and Distributed Processing, 2001. Proceedings. Ninth Euromicro Workshop on, 2001. »»
    Abstract

    conference paper / id: 2285870

    Content-based information retrieval using an embedded neural associative memory

    Schmidt, M.; Rückert, Ulrich

    In this paper a novel approach for the storage and access of an index used in internet search engines (Information Retrieval) is presented. The index provides a mapping from search terms to documents. The Binary Neural Associative Memory (BiNAM) stores an index by associating document signatures and document locations in a distributed and content addressable way. The system presented here has a high memory efficiency of more than 90%. The trade-off between memory consumption and precision of the query-results is examined. A scalable system architecture is presented. The architecture exploits the parallel structure of the BiNAM. The association time is estimated to be orders of magnitude faster than a software solution. The system is realized as a modular PCI architecture. The maximum capacity of the first version is 768MByte memory which allows to implement a BiNAM of 80k neurons with 80k inputs each. In such a system approximately 64 million associations can be stored and accessed within 330ns per association.


    In: Parallel and Distributed Processing, 2001. Proceedings. Ninth Euromicro Workshop on, 2001.
  • Witkowski, Ulf; Heittmann, Arne; Rückert, Ulrich:
    Hardware Implementation of Self-Organizing Maps and Associative Memory on the Minirobot Khepera.
    In: Autonomous Minirobots for Research and Edutainment – AMiRE 2001, 2001. »»

    conference paper / id: 2288451

  • Iske, Burkhard; Rückert, Ulrich:
    Cooperative Cube Clustering using Local Communication.
    In: Autonomous Robots for Research and Edutainment – AMiRE 2001, Proceedings of the 5th International Heinz Nixdorf Symposium, 2001. »»

    conference paper / id: 2288463

  • Löffler, Axel; Klahold, Jürgen; Rückert, Ulrich; Rückert, Ulrich; Sitte, Joaquin; Witkowski, Ulf:
    The Mini-Robot Khepera as a Foraging Animate: Synthesis and Analysis of Behaviour.
    In: Proceedings of the 5th International Heinz Nixdorf Symposium: Autonomous Minirobots for Research and Edutainment (AMiRE01), Volume: 97, Heinz Nixdorf Institut, Universität Paderborn, 2001. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2288475

    The Mini-Robot Khepera as a Foraging Animate: Synthesis and Analysis of Behaviour

    Löffler, Axel; Klahold, Jürgen; Rückert, Ulrich

    The work presented in this paper deals with the development of a methodology for resource-efficient behaviour synthesis on autonomous systems. In this context, a definition of a maximal problem with respect to the resources of a given system is introduced. It is elucidated by means of an exemplary implementation of the solution to such a problem using the mini-robot Khepera as the experimental platform. The described task consists of exploring an unknown and dynamically changing environment, collecting and transporting objects, which are associated with light-sources, and navigating to a home-base. The critical point is represented by the accumulated positioning errors in odometrical path-integration due to slippage. Therefore, adaptive sensor calibration using a specific variant of Kohonen’s algorithm is applied in two cases to extract symbolic, e.g. geometric, information from the sub-symbolic sensor data, which is used to enhance position control by landmark mapping and orientation. In order to successfully handle the arising complex interactions, a heterogeneous control-architecture based on a parallel implementation of basic behaviours coupled by a rule-based central unit is proposed.


    In: Proceedings of the 5th International Heinz Nixdorf Symposium: Autonomous Minirobots for Research and Edutainment (AMiRE01), Volume: 97, Heinz Nixdorf Institut, Universität Paderborn, 2001.
  • Porrmann, Mario; Rückert, Ulrich; Landmann, Jörg; Marks, Karl Michael:
    XipChip – A Multiprocessor CPU for Multifunction Peripherals.
    In: Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), Volume: 15, 2001. »»

    conference paper / id: 2288526

  • Iske, Burkhard; Rückert, Ulrich:
    Performance Analysis of a Colony of Locally Communicating Robots.
    In: Autonomous Mini Robots for Research and Edutainment – AMiRE 2001, Proceedings of the 5th International Heinz Nixdorf Symposium, 2001. »»
    Abstract

    conference paper / id: 2288467

    Performance Analysis of a Colony of Locally Communicating Robots

    Iske, Burkhard; Rückert, Ulrich

    A cube clustering problem which is to be solved by a colony of locally communicating robots is introduced. The performance of the robot colony solving the cube clustering problem is analysed regarding the number of £nal cluster points and the optimal robot density that solves the problem the fastest. Parallel computing theory is applied to determine the optimal robot density. The modelled performance matches with experiments executed with the minirobot Khepera.


    In: Autonomous Mini Robots for Research and Edutainment – AMiRE 2001, Proceedings of the 5th International Heinz Nixdorf Symposium, 2001.
  • Porrmann, Mario; Rüping, Stefan; Rückert, Ulrich:
    The Impact of Communication on Hardware Accelerators for Neural Networks.
    In: Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI), Volume: 3, 2001. »»

    conference paper / id: 2288549

  • Klahold, Jürgen; Rautenberg, Jens; Rückert, Ulrich; Rückert, Ulrich; Sitte, Joaquin; Witkowski, Ulf:
    Demonstration of an Ultrasonic Sensor for Mobile Minirobots Using Pseudo-Random Codes.
    In: Proceedings of the 5th International Heinz Nixdorf Symposium: Autonomous Minirobots for Research and Edutainment (AMiRE01), Volume: 97, Heinz Nixdorf Institut, Universität Paderborn, 2001. »»
    Abstract

    conference paper / id: 2288492

    Demonstration of an Ultrasonic Sensor for Mobile Minirobots Using Pseudo-Random Codes

    Klahold, Jürgen; Rautenberg, Jens; Rückert, Ulrich

    Ultrasonic sensor arrays enable autonomous robots to explore the multidimensional space of their immediate surroundings. The aim of the demonstration is to show to what extent a 5cm broad array of three piezo-ceramic ultrasonic transducers is appropriate for getting two-dimensional impressions of the surroundings. Therefore, deviating from the pulse echo measurement techniques used so far, the time-continuous transmitting and receiving from modulated pseudo-random sequences are used. Thus the narrow bandwidth of a piezo-ceramic transducer can be compensated by an increased measuring period. Furthermore, the application of several robots in joined surroundings without interference will be possible, if suitable sequences are selected and appropriate correlation measuring procedures are used. Different software tools for the two-dimensional interpretation of the measured data show the efficiency as well as the limits of the demonstrated sensor.


    In: Proceedings of the 5th International Heinz Nixdorf Symposium: Autonomous Minirobots for Research and Edutainment (AMiRE01), Volume: 97, Heinz Nixdorf Institut, Universität Paderborn, 2001.
  • Niemann, Jörg-Christian; Witkowski, Ulf; Porrmann, Mario; Rückert, Ulrich:
    Extension Module for Application-Specific Hardware on the Minirobot Khepera.
    In: Autonomous Minirobots for Research and Edutainment (AMiRE 2001), 2001. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2288555

    Extension Module for Application-Specific Hardware on the Minirobot Khepera

    Niemann, Jörg-Christian; Witkowski, Ulf; Porrmann, Mario; Rückert, Ulrich

    In this paper a hardware extension for the minirobot Khepera is presented. We are researching into algorithms for neural data processing and their hardware implementation by increasingly using the minirobot Khepera. This robot is supposed to record its environment continuously and to map obstacles. This is the basis for the implementation of an efficient navigational system. As the algorithms in question are complex and since the microcontroller on the Khepera does not possess the necessary processing capacity, it is requisite to develop a discrete hardware module that extends the Khepera.


    In: Autonomous Minirobots for Research and Edutainment (AMiRE 2001), 2001.
  • Klahold, Jürgen; Rautenberg, Jens; Rückert, Ulrich; Rückert, Ulrich; Sitte, Joaquin; Witkowski, Ulf:
    Ultrasonic Sensor for Mobile Mini-Robots Using Pseudo-Random Codes.
    In: Proceedings of the 5th International Heinz Nixdorf Symposium: Autonomous Minirobots for Research and Edutainment (AMiRE01), Volume: 97, Heinz Nixdorf Institut, Universität Paderborn, 2001. »»
    Fulltext (PDF)

    conference paper / id: 2288504

  • Hunstock, Ralf; Rückert, Ulrich; Hanna, Thomas:
    Implementation and Analysis of Mobile Agents in a Simulation Environment for Fieldbus Systems.
    In: Proccedings of the 2001 International Conference on Intelligent Agent Technology (IAT-01), 2001. »»
    Fulltext (external) Abstract

    conference paper / id: 2288457

    Implementation and Analysis of Mobile Agents in a Simulation Environment for Fieldbus Systems

    Hunstock, Ralf; Rückert, Ulrich; Hanna, Thomas

    Internet-agents, agents in local area networks or agents in factory production planning e.g. are well known and become more and more popular. The basic technologies which carry the agent technology often base upon JAVA or special agent languages as software and personal-, industrial- or embedded computers and their related network technologies. In the upcoming field of home- and building automation, special, dedicated hard- and software is utilised, called fieldbus systems. Fieldbus systems are equal to computers and computer networks in structure but have restrictions in resources and performance. Mobile agent technology also seems to be an appropriate paradigm for typical applications of building automation. In this paper we present the implementation of a basic agent system in an existing software simulator for a special fieldbus technology. We performed an analysis upon this implementation which indicated that this technology has advantages in fieldbus systems as well.


    In: Proccedings of the 2001 International Conference on Intelligent Agent Technology (IAT-01), 2001.
  • Porrmann, Mario; Kalte, Heiko; Witkowski, Ulf; Niemann, Jörg-Christian; Rückert, Ulrich:
    A Dynamically Reconfigurable Hardware Accelerator for Self-Organizing Feature Maps.
    In: Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics, SCI 2001, Volume: 3, 2001. »»
    Abstract

    conference paper / id: 2288539

    A Dynamically Reconfigurable Hardware Accelerator for Self-Organizing Feature Maps

    Porrmann, Mario; Kalte, Heiko; Witkowski, Ulf; Niemann, Jörg-Christian; Rückert, Ulrich

    A hardware accelerator for self-organizing feature maps is presented. The system is based on the universal rapid prototyping system RAPTOR2000 that has been developed by the authors. The prototyping system consists of a motherboard and up to six application specific modules. The motherboard provides the necessary communication infrastructure for the application specific functionality that is implented on the modules. RAPTOR2000 is linked to its host - a standard personal computer or workstation - via PCI bus. For the simulation of self-organizing maps a module has been disigned for the RAPTOR2000 system, that embodies an FPGA of the Xilinx Virtex series and optionally up to 128 MBytes of SDRAM. A speed-up of about 60 is achieved with five FPGA modules on the RAPTOR2000 system compared to a software implementation on a state of the art personal computer for typical applications of self-organizing maps.


    In: Proceedings of The 5th World Multi-Conference on Systemics, Cybernetics and Informatics, SCI 2001, Volume: 3, 2001.
2000
  • Vonnahme, E.; Ruping, S.; Rückert, Ulrich:
    Measurements in switched Ethernet networks used for automation systems.
    In: Factory Communication Systems, 2000. Proceedings. 2000 IEEE International Workshop on, 2000. »»
    Abstract

    conference paper / id: 2286162

    Measurements in switched Ethernet networks used for automation systems

    Vonnahme, E.; Ruping, S.; Rückert, Ulrich

    Ethernet networks for automation systems promise stundardized interworking between completely different devices fromjeld level up to ofice level without connection and conversion dificulties. As Ethernet was not originally developed considering automation system requirements, its qualijication, especially regarding topology and determinism demands, has to be examined. In this paper theoretical calculations on topology in& ence are completed by measurements on switch hardware. A speciul software for conjguring, monitoring and testing the switch hardware was developed. Further experiments for the evaluation of the Ethernet Medium Access Control Pause operation in automation systems are also described.


    In: Factory Communication Systems, 2000. Proceedings. 2000 IEEE International Workshop on, 2000.
  • Iske, B.; Rückert, Ulrich; Malmstrom, K.; Sitte, J.:
    A bootstrapping method for autonomous and in site learning of generic navigation behaviour.
    In: Pattern Recognition, 2000. Proceedings. 15th International Conference on, Volume: 4, 2000. »»
    Abstract

    conference paper / id: 2286256

    A bootstrapping method for autonomous and in site learning of generic navigation behaviour

    Iske, B.; Rückert, Ulrich; Malmstrom, K.; Sitte, J.

    To understand the behaviour of natural autonomous systems, research is carried out on artificial autonomous agents. This paper focuses on how simple behaviours can be learnt autonomously using a bootstrapping method. Firstly, a two dimensional Self-Organising Map is realised which provides the agent's sense of orientation. Once this relative positioning system has been established, the agent learns to navigate towards a target using the reinforcement learning technique of Q-Learning. Since only neural network processing is used, this technique emulates the distributed and adaptive information processing found in natural autonomous systems. Furthermore, due to its generality, the neural implementation developed is transferable to other artificial autonomous agents with different sensors and effector suites.


    In: Pattern Recognition, 2000. Proceedings. 15th International Conference on, Volume: 4, 2000.
  • Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
    Rapid Prototyping System für dynamisch rekonfigurierbare Hardwarestrukturen.
    In: Workshop: Architekturentwurf und Entwicklung eingebetteter Systeme (AES2000), 2000. »»

    conference paper / id: 2286566

  • Brinkmann, André; Langen, Dominik; Rückert, Ulrich:
    A Rapid Prototyping Environment for Microprocessor based System-on-Chips and its Application to the Development of a Network Processor.
    In: Proceedings of the 10th International Conference on Field Programmable Logic and Applications (FPL 2000), 2000. »»
    Abstract

    conference paper / id: 2286578

    A Rapid Prototyping Environment for Microprocessor based System-on-Chips and its Application to the Development of a Network Processor

    Brinkmann, André; Langen, Dominik; Rückert, Ulrich

    The rapid advances in microelectronic circuit design have dramatically increased the design complexity of modern integrated devices. One approach to fit the time-to-market requirements is the use of rapid prototyping environments. In this paper we introduce a new FPGA based prototyping environment, on which a full functional embedded system can be implemented. The main distinction to other environments is the incorporation of a synthesizable and configurable microprocessor core into the design space. Furthermore we present the application of this environment to the development of a network processor which consists of a processor core and an Ethernet controller.


    In: Proceedings of the 10th International Conference on Field Programmable Logic and Applications (FPL 2000), 2000.
  • Langen, D.; Brinkmann, A.; Rückert, Ulrich:
    High level estimation of the area and power consumption of on-chip interconnects.
    In: ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000. »»
    Abstract

    conference paper / id: 2286370

    High level estimation of the area and power consumption of on-chip interconnects

    Langen, D.; Brinkmann, A.; Rückert, Ulrich

    This paper addresses the problem of estimating the power and area consumption of on-chip interconnects for standard cell ASIC processes. We introduce a set of analytic investigations on buses, crossbar switches, and multiplexors. Furthermore we prove the accuracy of the results by comparing them with gate-level powerestimations on a double metal 0.6μm CMOS technology.


    In: ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000.
  • Kalte, Heiko; Porrmann, Mario; Rückert, Ulrich:
    Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics.
    In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA´2000), Volume: 5, 2000. »»

    conference paper / id: 2286572

  • Langen, Dominik; Brinkmann, André; Rückert, Ulrich:
    Abschätzung des Flächen- und Energieverbrauchs von Verbindungsstrukturen auf einem Chip.
    In: Proceedings of the ITG Workshop Mikroelektronik für die Informationstechnik, 2000. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2286584

    Abschätzung des Flächen- und Energieverbrauchs von Verbindungsstrukturen auf einem Chip

    Langen, Dominik; Brinkmann, André; Rückert, Ulrich

    Diese Arbeit befaßt sich mit der Aufgabe, den Energie- und Flächenverbrauch von Verbindungsstrukturen auf einem Chip für Standardzellen-Prozesse auf einer hohen Abstraktionsebene abzuschätzen. Es werden analytische Untersuchungen bezüglich der Verbindungsstrukturen Bus, Crossbar-Switch und Multiplexer vorgestellt und mit den Ergebnissen einer Simulation für eine 0,6 μm CMOS Technologie verglichen. Bezüglich der Abschätzung des Energieverbrauchs ergab sich ein mittlerer Fehler von etwa 10%.


    In: Proceedings of the ITG Workshop Mikroelektronik für die Informationstechnik, 2000.
  • Hunstock, R.; Ruping, S.; Rückert, Ulrich:
    A distributed simulator for large networks used in building automation systems.
    In: Factory Communication Systems, 2000. Proceedings. 2000 IEEE International Workshop on, 2000. »»
    Abstract

    conference paper / id: 2285890

    A distributed simulator for large networks used in building automation systems

    Hunstock, R.; Ruping, S.; Rückert, Ulrich

    In modem building automation systems an increasing number of devices with computational facilities exchange data and interoperate using underlying control networks. Discontinuous and non-linear processes, synchronization effects and delays in communication lead to systems with highly complex behavior: Analytical methods ofen do not meet the demands for the evaluation of such systems. As an alternative approach discrete event simulation gains more and more importance. In this paper we present the development of a distributed software simulator especially designed for large automation systems consisting of thousands of microcontroller based devices. An existing and expanding building automation system used to validate the simulator and which forms a base for modeling a large system is also described.


    In: Factory Communication Systems, 2000. Proceedings. 2000 IEEE International Workshop on, 2000.
  • Brinkmann, André; Langen, Dominik; Rückert, Ulrich:
    Aktive Router: Ein Hardwarekonzept für Storage Area Networks.
    In: Proceedings of the ITG Workshop Mikroelektronik für die Informationstechnik, 2000. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2286590

    Aktive Router: Ein Hardwarekonzept für Storage Area Networks

    Brinkmann, André; Langen, Dominik; Rückert, Ulrich

    Die Verschaltung von Festplatten zu Feldern zur effizienten Verwaltung von riesigen Datenmengen gewinnt immer mehr an Bedeutung. Durch den Einsatz aktiver Einheiten zum Aufbau von internen Verbindungsstrukturen zwischen den Festplatten ist es möglich, an das System angeschlossene Dateiserver von vielen Basisaufgaben zu entlasten. Diese aktiven Router basieren neben einer Routingeinheit und den Schnittstellen zu den Festplatten und den Dateiservern auf einem Mikroprozessor und einer rekonfigurierbaren Einheit. Im Rahmen dieser Arbeit werden mögliche Einsatzgebiete von aktiven Routern, Untersuchungen zu deren Dimensionierung und praktischen Implementierungen der Hardware vorgestellt.


    In: Proceedings of the ITG Workshop Mikroelektronik für die Informationstechnik, 2000.
1999
  • Löffler, Axel; Mondada, Francesco; Rückert, Ulrich:
    Proceedings of the 1st International Khepera Workshop: Experiments with the Mini-Robot Khepera.
    In: Volume: 64, Heinz Nixdorf Institut, Universität Paderborn, 1999. »»

    conference publication / id: 2285604

  • Loffler, A.; Klahold, J.; Heittmann, A.; Witkowski, U.; Rückert, Ulrich:
    Implementing Neural Soft- And Hardware On The Autonomous Mini-robot Khepera.
    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999. »»
    Abstract

    conference paper / id: 2285983

    Implementing Neural Soft- And Hardware On The Autonomous Mini-robot Khepera

    Loffler, A.; Klahold, J.; Heittmann, A.; Witkowski, U.; Rückert, Ulrich

    The applicability of neural networks to generate complex behaviour on autonomous systems is demonstrated both at soft- and hardware-level. In particular, the emergence of simple behaviors based on the Braitenberg approach, adaptive sensor calibration by self-organizing maps with a comparison between off- and online learning and a visualisation tool for a posteriori analysis are shown. It is also envisaged to present the working of embedded neural hardware as associative memory and self-organizing maps. In this connection, the mini-robot Khepera serves as an exemplary platform


    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999.
  • Rüping, Stefan; Löffler, Axel; Odenbach, Christopher; Rückert, Ulrich; Löffler, Axel; Mondada, Francesco; Rückert, Ulrich:
    Khepera Module for Wireless Infrared CAN Communication.
    In: Proceedings of the 1st International Khepera Workshop: Experiments with the Mini-Robot Khepera (IKW99), Volume: 64, 1999. »»

    conference paper / id: 2286518

  • Löffler, Axel; Klahold, Jürgen; Hußmann, Manfred; Rückert, Ulrich; Floreano, Dario; Nicoud, Jean-Daniel; Mondada, Francesco:
    A Visualization Tool for the Mini-Robot Khepera: Behaviour Analysis and Optimization.
    In: Proceedings of the 5th International European Conference on Artificial Life (ECAL99), Volume: 1674, Springer-Verlag, 1999. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2286532

    A Visualization Tool for the Mini-Robot Khepera: Behaviour Analysis and Optimization

    Löffler, Axel; Klahold, Jürgen; Hußmann, Manfred; Rückert, Ulrich

    The design of behavior generating control structures for real robots acting autonomously in a real and changing environment is a complex task. This is in particular true with respect to the debugging process, the documentation of the encountered behavior, its quantitative analysis and the final evaluation. To successfully implement such a behavior, it is vital to couple the synthesis on a simulator and the experiment on a real robot with a thorough analysis. The available simulator tools in general only allow behavioral snapshots and do not provide the option of online interference. In order to cure these shortcomings, a visualization tool for aposteriori graphical analysis of recorded data sets which gives access to all relevant internal states and parameters of the system is presented. The mini-robot Khepera has been chosen as experimentatory platform.


    In: Proceedings of the 5th International European Conference on Artificial Life (ECAL99), Volume: 1674, Springer-Verlag, 1999.
  • Porrmann, Mario; Ruping, S.; Rückert, Ulrich:
    SOM hardware with acceleration module for graphical representation of the learning process.
    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999. »»
    Abstract

    conference paper / id: 2286315

    SOM hardware with acceleration module for graphical representation of the learning process

    Porrmann, Mario; Ruping, S.; Rückert, Ulrich

    A digital hardware implementation of self-organizing maps is presented. Dedicated hardware is implemented that allows the on-line visualization of the map during learning. The use of a scalable parallel architecture enables the realization of large scale high performance maps. Fist silicon was produced in a 0.8 mm, 2 metal layer CMOS technology, implementing about 161,800 transistors on a die size of 28.58 mm 2 . Experimental results are presented, that prove the functionality of the design up to a clock frequency of 40 MHz. A classification rate of 250,000 vectors per second and an adaptation rate of 94,000 vectors per second can be guaranteed, independent from the size of the network.


    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999.
  • Witkowski, Ulf; Heittmann, Arne; Rückert, Ulrich:
    Implementation of Application Specific Neural Hardware on the Mini Robot Khepera.
    In: Proceedings of the 1st International Khepera Workshop, Volume: 64, Heinz Nixdorf Institut, Universität Paderborn, 1999. »»

    conference paper / id: 2286512

  • Heittmann, A.; Rückert, Ulrich:
    Mixed mode VLSI implementation of a neural associative memory.
    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999. »»
    Abstract

    conference paper / id: 2285828

    Mixed mode VLSI implementation of a neural associative memory

    Heittmann, A.; Rückert, Ulrich

    A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a n×m matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. Although analog circuits suffer from device mismatch a moderate precision of the circuit is acceptable since for the given associative memory model only few parts of the circuit participate on the performed information processing steps. Thus, the information processing elements can be integrated very densely on one chip and hence large scale integration with a large number of connection weights is feasible


    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999.
  • Klahold, Jürgen; Löffler, Axel; Rückert, Ulrich; Löffler, Axel; Mondada, Francesco; Rückert, Ulrich:
    Discrete Ultrasonic Sensors for Mobile Autonomous Systems.
    In: Proceedings of the 1st International Khepera Workshop: Experiments with the Mini-Robot Khepera (IKW99), Volume: 64, Heinz Nixdorf Institut, Universität Paderborn, 1999. »»
    Abstract

    conference paper / id: 2286554

    Discrete Ultrasonic Sensors for Mobile Autonomous Systems

    Klahold, Jürgen; Löffler, Axel; Rückert, Ulrich

    Ultrasonic enables a mobile autonomous system to obtain information about obstacles in large environments. In the presented work, taking the limited energy resources of a mobile robot into account, only one transmitter is used. The employment of two receivers permits the calculation of the distance to and the orientation of a wall, using only time-of-flight measurements. The evaluation procedure consists of basic geometrical calculations, which do not strain the system's calculating power too excessively. The results show that it is possible to place the transmitter and the receivers close together without losing much of the performance. Hence the introduced arrangement of ultrasonic sensors can be used for small systems, e.g. the mini-robot Khepera.


    In: Proceedings of the 1st International Khepera Workshop: Experiments with the Mini-Robot Khepera (IKW99), Volume: 64, Heinz Nixdorf Institut, Universität Paderborn, 1999.
  • Korner, T.; Sitte, J.; Rückert, Ulrich:
    An analog local cluster neural net for a 3 V supply.
    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999. »»
    Abstract

    conference paper / id: 2285822

    An analog local cluster neural net for a 3 V supply

    Korner, T.; Sitte, J.; Rückert, Ulrich

    The local cluster neural net (LC net) is a feedfoward net suitable for continuous function approximation and discrete classification tasks. All operations of the LC net can be realized in analog circuits. Therefore we implemented the LC net in analog VLSI hardware for a 3 V power supply. Main applications of the LC net are control tasks in autonomous systems that can be battery powered. In this paper we describe the CMOS VLSI realization and present the results of the comprehensive test measurement for characterising the performance of the implementation


    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999.
  • Wolff, C.; Hartmann, G.; Rückert, Ulrich:
    ParSPIKE-a parallel DSP-accelerator for dynamic simulation of large spiking neural networks.
    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999. »»
    Abstract

    conference paper / id: 2285834

    ParSPIKE-a parallel DSP-accelerator for dynamic simulation of large spiking neural networks

    Wolff, C.; Hartmann, G.; Rückert, Ulrich

    The fast simulation of large networks of spiking neurons is a major task for the examination of biology inspired vision systems. Networks of this type are labelling features by synchronization of spikes and there is strong demand to simulate those effects in a real world environment. Because of the quite complex calculations for one model neuron the simulation of thousands or millions of these neurons is not efficient on existing hardware platforms. In order to simulate closer to the real time requirement, it is necessary to implement a dedicated hardware. Our aim is a hardware system mainly consisting of standard components which is as flexible as possible concerning the model neuron but as specialized as necessary to meet our performance requirements. Thus we decided to implement a parallel system with Digital Signal Processors (DSP) offering a large on-chip-memory. One main task of this work is the optimization of the simulation algorithm for the neurons distributed to the DSP which means the sequential part of simulation. This optimization benefits from the fact that there is only a very low percentage of simultaneously active neurons in vision networks. For communication between the nodes only spikes are distributed via a spike switching network. Processing of the network topology is realized by two different concepts. One idea is to compute the synapses autonomously on the processing node by representing a regular connection scheme with one connection mask for many neurons. Additional connections requiring adaptability and irregular connection schemes are stored in a shared memory. To avoid a bottleneck a synapse caching is used within each processing node. This paper describes the architecture of a DSP accelerator and shows the advantages with simulation results from a typical large vision network


    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999.
  • Loffler, A.; Klahold, J.; Rückert, Ulrich:
    Artificial neural networks for autonomous robot control: reflective navigation and adaptive sensor calibration.
    In: Neural Information Processing, 1999. Proceedings. ICONIP '99. 6th International Conference on, Volume: 2, 1999. »»
    Abstract

    conference paper / id: 2286344

    Artificial neural networks for autonomous robot control: reflective navigation and adaptive sensor calibration

    Loffler, A.; Klahold, J.; Rückert, Ulrich

    In this paper, we present the application of artificial neural networks to the control of a mobile, autonomous robot, which is acting in a totally unknown and - most importantly - dynamically changing environment. In particular, the employment of interacting 'simple', i.e. hand-designed, neural networks for navigation purposes is investigated as well as a variation of self-organizing maps for adaptive sensor calibration. We insofar take a pragmatic point of view as the minimal condition imposed on the developed algorithms is that they do well on a real system acting in a real environment. Hence, the design of all of the implemented neural networks is clearly motivated by their applicability. In this context, special considerations are dedicated to ensure robustness, real-time capability and memory resourcefulness. In order to practically demonstrate the obtained results, the minirobot Khepera is utilized as an experimentatory platform, which is - due to its small size - a versatile tool for scientific investigation.


    In: Neural Information Processing, 1999. Proceedings. ICONIP '99. 6th International Conference on, Volume: 2, 1999.
  • Löffler, Axel; Klahold, Jürgen; Hußmann, Manfred; Rückert, Ulrich:
    Demonstration of a Visualization Tool for the Mini-Robot Khepera.
    In: Web publication of the 5th International European Conference on Artificial Life (ECAL), 1999. »»

    conference paper / id: 2286546

  • Grotstollen, H; Schütte, F.; Rückert, Ulrich; Witkowski, U.:
    Lernfähige, selbsteinstellende Antriebsregelung mit Hilfe neuronaler Hardware.
    In: 1999. »»

    report / id: 2285763

  • Witkowski, U.; Neumann, T.; Rückert, Ulrich:
    Digital hardware realization of a hyper basis function network for on-line learning.
    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999. »»
    Abstract

    conference paper / id: 2286127

    Digital hardware realization of a hyper basis function network for on-line learning

    Witkowski, U.; Neumann, T.; Rückert, Ulrich

    The proposed paper describes a digital neural network hardware realization performing a hyper basis function network for function approximation. Both, learning and recall of the network are implemented in hardware to achieve a high performance network calculation. This opens the use of the function approximator to applications with real-time learning requirements for on-line learning. The presented hardware uses a flexible network structure, i.e. the number of basis functions is not fixed in advance, but they are integrated into the network during learning depending on the learning data set. Thus, we have a good approximation result by using a minimal number of basis functions


    In: Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on, 1999.
1998
  • Rüping, Stefan; Lücking, Wilfried; Rückert, Ulrich:
    A Wireless Communication System for Khepera Micro-Robots using CAN.
    In: Proceedings of the European Telemetry Conference (ETC98), 1998. »»

    conference paper / id: 2286455

  • Löffler, Axel; Klahold, Jürgen; Rückert, Ulrich; Hao, Jin-Kao; Lutton, Evelyne; Ronald, Edmund; Schoenauer, Marc; Snyers, Dominique:
    The Dynamical Nightwatch's Problem Solved by the Autonomous Micro-Robot Khepera.
    In: Selected Papers of the 3rd European Conference on Artificial Evolution (AE97), Volume: 1363, Springer-Verlag, 1998. »»
    Fulltext (PDF) Abstract

    conference paper / id: 2286486

    The Dynamical Nightwatch's Problem Solved by the Autonomous Micro-Robot Khepera

    Löffler, Axel; Klahold, Jürgen; Rückert, Ulrich

    In this paper, we present the implementation, both in a simulator and in a real-robot version, of an efficient solution to the so-called dynamical nightwatch’s problem on the micro-robot Khepera. The problem consists mainly in exploring a previously unknown environment while detecting, registering and recognizing light sources which may dynamically be turned on and off. At the end of each round a report is requested from the robot. Therein we made use of an agent-based approach and applied a self-organizing feature map in order to refine some of the behaviour generating control-modules.


    In: Selected Papers of the 3rd European Conference on Artificial Evolution (AE97), Volume: 1363, Springer-Verlag, 1998.
  • Rückert, Ulrich; Haan, Oswald:
    Hardware-Realisierung neuronaler Netze.
    In: Göttinger Informatik Kolloquium – Vorträge aus den Jahren 1996/97, 1998. »»

    conference paper / id: 2285586

  • Sitte, Joaquin; Körner, Tim; Rückert, Ulrich:
    Local Cluster Neural Net: Analog VLSI Design.
    In: Neurocomputing, Volume: 19, 1998. »»
    Abstract

    article / id: 2285598

    Local Cluster Neural Net: Analog VLSI Design

    Sitte, Joaquin; Körner, Tim; Rückert, Ulrich

    The local cluster (LC) artificial neural net is a special kind of multilayer perceptron where the sigmoid functions combine in clusters that have a localised response in input space. The proponents of the LC architecture have shown that it is versatile and trains well. They also suggested that the LC nets could be suitable for realisation in analog VLSI. We investigated the feasibility of an analog realisation of LC nets by following through the complete cycle from design to fabrication. We found that all the required mathematical functions for an analog realisation of LC net can be realised in current mode bipolar and CMOS circuits. In this paper we discuss the main design issues paying special attention to the alternative training regimes for a LC chip.


    In: Neurocomputing, Volume: 19, 1998.
  • Fuchs, Bernhard; Vogel, Sven; Schröder, Dietmar; Paul, Reinhold; Rückert, Ulrich:
    Autonome EKG-Elektrode zur kabellosen Patientenüberwachung.
    In: Mikroelektronik für die Informationstechnik, 1998. »»
    Abstract

    conference paper / id: 2286476

    Autonome EKG-Elektrode zur kabellosen Patientenüberwachung

    Fuchs, Bernhard; Vogel, Sven; Schröder, Dietmar; Paul, Reinhold; Rückert, Ulrich

    Im folgenden wird über die Entwicklung integrierter Schaltkreise in 0,8 µm CMOS Technologie zur Gewinnung und Übermittlung von Biosignalen, wie zum Beispiel dem Elektrokardiogramm (EKG), der Atemtätigkeit des Brustkorbes, der Blutsauerstoffsättigung oder dem Elektroenzephalogramm (EEG) berichtet. Ein Ziel dieser Arbeit ist die autonome EKG-Elektrode, die aufgrund ihrer kompakten Größe und geringer Leistungsaufnahme, durch den Einsatz anwendungsspezifischer IC's, komplett (mit Stromversorgung, gesamter Elektronik und den Elektrodenkontakten zur Haut) auf den Patient en als Pflasterelektrode aufgeklebt werden kann. Dadurch werden Langzeit- oder Belastungsst udien in der medizinischen Diagnostik komfortabler und zuverlässiger. Das gilt besonde rs für den Bereich der Säuglingsüberwachung (z.B. bei der Vermeidung des plötzlichen Kindstodes).


    In: Mikroelektronik für die Informationstechnik, 1998.
  • Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich:
    SOM Accelerator System.
    In: Neurocomputing, Volume: 21, 1998. »»
    Fulltext (external) Abstract

    article / id: 2285592

    SOM Accelerator System

    Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich

    Many applications of self-organizing maps (SOM) require high computing performance in order to be efficient. Because of the regular and modular structure of SOMs, a custom hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this article a high-performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit (ES2 1.0 μm CMOS) contains 25 processing elements in a 5×5 array. Due to the scalability of the chips a VMEbus board was built with 16 ICs on it. The controllers for the VMEbus and the SOM hardware are realized using FPGAs. The system runs SOM applications with up to 400 elements in parallel mode (20×20 map). Each model vector can have up to 64 weights of 8 bit accuracy. The maximum performance of the board-system is 4.1 GCPS (recall) and 2.4 GCUPS (learning). It is integrated in a simulation framework for neural networks, that contains software tools for self-organizing maps as well as for neural associative memories, tools for pre- and postprocessing and tools for graphical analysis of the simulation results.


    In: Neurocomputing, Volume: 21, 1998.
  • Porrmann, Mario; Heittmann, Arne; Rüping, Stefan; Rückert, Ulrich:
    A Hybrid Knowledge Processing System.
    In: Proceedings of the Conference Neural Networks and their Applications (NEURAP), 1998. »»

    conference paper / id: 2286468

  • Rückert, Ulrich; Witkowski, Ulf; Niklasson, L.; Bodén, M.; Ziemke, T.:
    Silicon Artificial Neural Networks.
    In: Proceedings of the Conference on Artificial Neural Networks, ICANN´98, Springer-Verlag, 1998. »»

    conference paper / id: 2286502

1997
  • Rückert, Ulrich:
    Integrationsgerechte parallele Systemkonzepte unter Ausnutzung spärlicher Interaktion am Beispiel neuronaler Netze.
    In: Heinz Nixdorf Institut, 1997. »»

    report / id: 2285584

  • Porrmann, Mario; Landmann, Jörg; Marks, Karl Michael; Rückert, Ulrich:
    HIBRIC-MEM, a Memory Controller for PowerPC Based Systems.
    In: Proceedings of the 23rd EUROMICRO Conference, 1997. »»
    Abstract

    conference paper / id: 2286241

    HIBRIC-MEM, a Memory Controller for PowerPC Based Systems

    Porrmann, Mario; Landmann, Jörg; Marks, Karl Michael; Rückert, Ulrich

    This paper describes the architecture and development of an innovative memory controller for the PowerPC family. HiBRIC-MEM (High Bandwidth Resource Intei$ace Controller) provides control for up to two PowerPC processors. A look-ahead mechanism, called stream cache, is used to reduce the effective memory latency and a 12-bit error correction code is available for optimal system security. Initial silicon was produced in a 0.7 pm, three metal layer Motorola technology and has a die size of 12.1 x 12.1 mm2. HiBRIC-MEM is used e.g. in a commercially available parallel computer.


    In: Proceedings of the 23rd EUROMICRO Conference, 1997.
  • Witkosski, U.; Ruping, S.; Rückert, Ulrich; Schutte, F.; Beineke, S.; Grotstollen, H.:
    System identification using selforganizing feature maps.
    In: Artificial Neural Networks, Fifth International Conference on (Conf. Publ. No. 440), 1997. »»
    Abstract

    conference paper / id: 2286012

    System identification using selforganizing feature maps

    Witkosski, U.; Ruping, S.; Rückert, Ulrich; Schutte, F.; Beineke, S.; Grotstollen, H.

    A method for identification of mechanical systems is reported. The identification of mechanical systems is often done by neural networks used as black boxes in order to produce an inverse system model for control. Contrary to this approach, we intend to identify the mechanical structure and parameters, which allows the use of conventional control theory. The basis of the identification system is a self-organizing feature map (SOFM) representing the systems to be identified. The systems are described by their response to test signals, which are used for feature extraction. The extracted features are analyzed with SOFMs to explore the feature space. The map is well suited for this kind of interpretation. As an application example, the identification of a two mass system is presented


    In: Artificial Neural Networks, Fifth International Conference on (Conf. Publ. No. 440), 1997.
  • Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich:
    A High Performance SOFM Hardware-System.
    In: Proceedings of the International Work-Conference on Artificial and Natural Neural Networks (IWANN´97), 1997. »»

    A High Performance SOFM Hardware-System

    Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich

    Many applications of Selforganizing Feature Maps (SOFMs) need a high performance hardware system in order to be efficient. Because of the regular and modular structure of SOFMs, a hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this paper a high performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit contains 25 processing elements in a 5 by 5 array. Due to the scalability of the chips a VME-bus board was built with 16 ICs on it. The controller for the VME-bus and the SOFM hardware are realized using FPGAs. The system runs SOFM applications with up to 400 elements in parallel mode (20 by 20 map). Each weight vector can have up to 64 weights of 8 bit accuracy. The maximum performance of the board-system is 4.1 GCPS (recall) and 2.4 GCUPS (learning).


    In: Proceedings of the International Work-Conference on Artificial and Natural Neural Networks (IWANN´97), 1997.
  • Schütte, Frank; Beineke, Stefan; Grotstollen, Horst; Witkowski, Ulf; Rückert, Ulrich; Rüping, Stefan:
    Structure- and Parameter Identification for a Two-Mass-System With Backlash and Friction Using a Self-Organizing Map.
    In: 7th European Conference on Power Electronics and Applications, EPE97, Volume: 3, 1997. »»
    Abstract

    conference paper / id: 2286390

    Structure- and Parameter Identification for a Two-Mass-System With Backlash and Friction Using a Self-Organizing Map

    Schütte, Frank; Beineke, Stefan; Grotstollen, Horst; Witkowski, Ulf; Rückert, Ulrich; Rüping, Stefan

    A self-commissioning system for high performance speed and position control of electrical drives requires a structure and parameter identification of a nonlinear mechanic as basic building block. This self-commisioning system in combination with a new identification scheme is presented here. The identification is based on extraction of characteristic features from the system response and evaluation of these features by self-organizing neural network, especially the self-organizing feature map (SOM).


    In: 7th European Conference on Power Electronics and Applications, EPE97, Volume: 3, 1997.
  • Körner, Tim; Hartmann, Torsten; Rückert, Ulrich; Sitte, Joaquin; Klar, H.; König, A.; Ramacher, Ulrich:
    An Analog Current Mode VLSI Local Cluster Neural Net.
    In: Proceedings of the 6th International Conference on Microelectronics for Neural Networks, Evolutionary and Fuzzy Systems, 1997. »»

    conference paper / id: 2286408

  • Körner, Tim; Geldreich, Stefan; Rückert, Ulrich; Kasper, K.; Reininger, H.; Wüst, H.; Klar, H.; König, A.; Ramacher, Ulrich:
    Implementation of a Locally Recurrent Neural Network for Speech Recognition.
    In: Proceedings of the 6th International Conference on Microelectronics for Neural Networks, Evolutionary and Fuzzy Systems, 1997. »»

    conference paper / id: 2286422

  • Heittmann, Arne; Malin, J.; Pintaske, Christoph; Rückert, Ulrich; Klar, H.; König, A.; Ramacher, Ulrich:
    Digital VLSI Implementation of a Neural Associative Memory.
    In: Proceedings of the 6th International Conference on Microelectronics for Neural Network, Evolutionary and Fuzzy Systems, 1997. »»

    conference paper / id: 2286441

  • Sitte, J.; Korner, T.; Rückert, Ulrich:
    An analog-current mode local cluster neural net.
    In: Emerging Technologies and Factory Automation Proceedings, 1997. ETFA '97., 1997 6th International Conference on, 1997. »»
    Abstract

    conference paper / id: 2285884

    An analog-current mode local cluster neural net

    Sitte, J.; Korner, T.; Rückert, Ulrich

    The local cluster (LC) artificial neural net is a special kind of multilayer perceptron where the sigmoid functions combine in clusters that have a localised response in input space. The proponents of the LC architecture have shown that it is versatile and trains well. They also suggested that the LC nets could be suitable for realisation in analog VLSI. We investigated the feasibility of an analog realisation of LC nets by following through the complete cycle from design to fabrication. We found that the all the required mathematical functions call be realised in current mode bipolar and CMOS circuits. In this paper we discuss the main design issues paying special attention to the alternative training regimes for an LC chip


    In: Emerging Technologies and Factory Automation Proceedings, 1997. ETFA '97., 1997 6th International Conference on, 1997.
  • Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich:
    SOM Hardware-Accelerator.
    In: Workshop on Self-Organizing Maps (WSOM), 1997. »»

    SOM Hardware-Accelerator

    Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich

    Many applications of Selforganizing Feature Maps (SOMs) need a high performance hardware system in order to be efficient. Because of the regular and modular structure of SOMs , a hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this paper a high performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit contains 25 processing elements in a 5 by 5 array. Due to the scalability of the chips a VME-bus board was built with 16 ICs on it. The controller for the VME-bus and the SOM hardware are realized using FPGAs. The system runs SOM applications with up to 400 elements in parallel mode (20 by 20 map). Each weight vector can have up to 64 weights of 8 bit accuracy. The maximum performance of the board-system is 4.1 GCPS (recall) and 2.4 GCUPS (learning).


    In: Workshop on Self-Organizing Maps (WSOM), 1997.
1996
  • Rüping, Stefan; Rückert, Ulrich; Goser, Karl; Hartung, M.:
    Diagnosis-Systems with Selforganizing Feature Maps and Fuzzy-Logic.
    In: Proceedings of the Conference on Neural Networks and their Applications (NEURAP), 1996. »»

    conference paper / id: 2285560

  • Rückert, Ulrich:
    Hardwareimplementierung Neuronaler Netze.
    In: Konnektionismus und Neuronale Netze Beiträge zur Herbstschule (HeKoNN96), 1996. »»

    conference paper / id: 2285568

  • Rüping, Stefan; Rückert, Ulrich:
    A Scalable Processor Array for Self-Organizing Feature Maps.
    In: Proceedings of the 6th International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro), IEEE Computer Society Press, 1996. »»
    Abstract

    conference paper / id: 2285570

    A Scalable Processor Array for Self-Organizing Feature Maps

    Rüping, Stefan; Rückert, Ulrich

    Selforganizing Feature Maps (SOFMs) can be applied for data analysis, controlling problems and pattern matching. In many cases the requirements of a system using these maps are high performance and small physical size. This leads to the necessity of custom chip designs. In this paper two chips are presented, that realize a scalable processor array for self-organizing feature maps. First the design and test results of a single processor chip are described. Based on these results a second chip has been developed implementing a 5 by 5 array of elements. Each processor has on-chip memory to store 64 weights of 8 bit. The calculation unit has an internal precision of 14 bit. An input pattern can have 64 vector components of 8 bit. In order to achieve high speed, all elements work in parallel. Several of this chips can be cascaded to larger map sizes in a system


    In: Proceedings of the 6th International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro), IEEE Computer Society Press, 1996.
  • Palm, Günther; Rückert, Ulrich; Porrmann, Mario; Schwenker, Friedhelm:
    Neuronale Assoziativspeicher.
    In: Neuroinformatik Statusseminar, 1996. »»

    conference paper / id: 2285575

  • Hartung, M.; Goser, Karl; Rückert, Ulrich:
    The associative matrix as a concept for intelligent memory chips.
    In: Proceedings of the Conference on Neural Networks and their Applications (NEURAP), 1996. »»

    conference paper / id: 2285554

1995
  • Körner, Tim; Rückert, Ulrich; Geva, Shlomo; Malmstrom, Kurt; Sitte, Joaquin:
    VLSI friendly neural network with localied transfer functions.
    In: Proceedings of the IEEE International Conference on Neural Networks, Volume: 1, 1995. »»

    conference paper / id: 2285538

  • Rückert, Ulrich; Goser, Karl:
    Wissensverarbeitung in neuronaler Architektur.
    In: Universität Dortmund und Universität Paderborn, 1995. »»

    report / id: 2285532

  • Rückert, Ulrich:
    Hardwareimplementierung Neuronaler Netze.
    In: Konnektionismus und Neuronale Netze, 1995. »»

    conference paper / id: 2285536

  • Rüping, Stefan; Goser, Karl; Rückert, Ulrich:
    A Chip for Selforganizing Feature Maps.
    In: IEEE Micro, Volume: 15, 1995. »»
    Abstract

    article / id: 2285548

    A Chip for Selforganizing Feature Maps

    Rüping, Stefan; Goser, Karl; Rückert, Ulrich

    The use of self-organizing feature maps in real-time applications requires a high computational performance. Especially for embedded systems neural network chips are needed. In this paper a fabricated integrated circuit for self-organizing feature maps is presented. The architecture of this digital chip is based on the idea, that restrictions to the algorithm can simplify the implementation. Using the Manhattan Distance and a special treatment of the adaptation factor α decreases the necessary chip area, so that a high number of processor elements can be integrated on one chip. The effects of these restrictions on the function of the self-organizing feature map are discussed. The paper concludes with performance figures for a system architecture based on these chips


    In: IEEE Micro, Volume: 15, 1995.
1994
  • Rückert, Ulrich:
    Hardwareimplementierung Neuronaler Netze.
    In: Konnektionismus und Neuronale Netze, 1994. »»

    conference paper / id: 2285507

  • Rückert, Ulrich; Rüping, Stefan; Naroska, E.; Delgado-Frias, J.G.; Moore, W.R.:
    Parallel Implementation of Neural Associative Memories on RISC Processors.
    In: VLSI for Neural Networks and Artificial Intelligence, Plenum Press, 1994. »»
    Fulltext (PDF)

    conference paper / id: 2285521

  • Rüping, Stefan; Rückert, Ulrich; Goser, Karl:
    A Chip for Selforganizing Feature Maps.
    In: Proceedings of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, IEEE Computer Society Press, 1994. »»
    Abstract

    conference paper / id: 2285498

    A Chip for Selforganizing Feature Maps

    Rüping, Stefan; Rückert, Ulrich; Goser, Karl

    The use of self-organizing feature maps in real-time applications requires a high computational performance. Especially for embedded systems neural network chips are needed. In this paper a fabricated integrated circuit for self-organizing feature maps is presented. The architecture of this digital chip is based on the idea, that restrictions to the algorithm can simplify the implementation. Using the Manhattan Distance and a special treatment of the adaptation factor α decreases the necessary chip area, so that a high number of processor elements can be integrated on one chip. The effects of these restrictions on the function of the self-organizing feature map are discussed. The paper concludes with performance figures for a system architecture based on these chips


    In: Proceedings of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems, IEEE Computer Society Press, 1994.
  • Rückert, Ulrich:
    A Hybrid Knowledge Processing Architecture.
    In: Proceedings of the 2nd IEE International Conference on Intelligent Systems Engineering, 1994. »»
    Abstract

    conference paper / id: 2285504

    A Hybrid Knowledge Processing Architecture

    Rückert, Ulrich

    An example of a hybrid system architecture integrating connectionist models and symbolic knowledge processing is introduced. In particular the inclusion of non-symbolic knowledge sources (data from physical processes, measurements, sensors etc.), transformation of learned knowledge into a symbolic form (rule extraction) and associative storage as well as retrieval of information are discussed by means of application examples. Finally, parallel hardware support for the proposed hybrid system architecture is presented


    In: Proceedings of the 2nd IEE International Conference on Intelligent Systems Engineering, 1994.
  • Palm, Günther; Goser, Karl; Rückert, Ulrich; Ultsch, Alfred; Delgado-Frias, J.G.; Moore, W.R.:
    Knowledge Processing in Neural Architecture.
    In: VLSI for Neural Networks and Artificial Intelligence, Plenum Press, 1994. »»

    conference paper / id: 2285509

1993
  • Rüping, Stefan; Rückert, Ulrich; Goser, Karl; Mira, J.; Cabestany, J.; Prieto, A.:
    Hardware Design for Selforganizing Feature Maps with Binary Inputs.
    In: New Trends in Neural Computation, Volume: 686, Springer-Verlag, 1993. »»
    Fulltext (PDF) Fulltext (external)

    conference paper / id: 2285464

  • Rückert, Ulrich:
    Microelectronic Implementation of Neural Networks.
    In: Aachener Beiträge zur Informatik, Volume: 3, 1993. »»

    conference paper / id: 2285462

  • Rückert, Ulrich; Funke, A.; Pintaske, Christoph:
    Acceleratorboard for Neural Associative Memories.
    In: Neurocomputing, Volume: 5, 1993. »»
    Fulltext (external) Abstract

    article / id: 2285486

    Acceleratorboard for Neural Associative Memories

    Rückert, Ulrich; Funke, A.; Pintaske, Christoph

    Describes a parallel and scalable architecture for rapid prototyping and fast emulation of neural associative memories (NAMs). The implementation is based on custom available components: RAMs and field programmable gate arrays (FPGAs). The use of FPGAs offers an alternative for parallel implementation of NAMs because the desired application can be realized very fast, and a flexible adjustment of the hardware to improved algorithms is possible without replacing chips. The developed accelerator board is designed as an ISA slot card for IBM-compatible PCs and can provide computational rates that are sufficient for the commercial implementation of a range of NAM applications. (PsycINFO Database Record (c) 2010 APA, all rights reserved)


    In: Neurocomputing, Volume: 5, 1993.
  • Rückert, Ulrich; Spaanenburg, Lambert; Anlauf, Joachim:
    Hardware-Implementierung Künstlicher Neuronaler Netze.
    In: atp – Automatisierungstechnische Praxis, 1993. »»

    conference paper / id: 2285478

  • Marks, Karl Michael; Rückert, Ulrich; Staudt von, H.-M.:
    Verfahren und Einrichtung zur fehlercodierenden Datenübertragung.
    In: 1993. »»
    Abstract

    patent / id: 2285492

    Verfahren und Einrichtung zur fehlercodierenden Datenübertragung

    Marks, Karl Michael; Rückert, Ulrich; Staudt von, H.-M.

    Die Erfindung betrifft ein Verfahren und eine Einrichtung zur Erkennung und/oder Korrektur von 1- und mehr-Bit-Fehlern gemäß Oberbegriff der Patentansprüche 1 und 5. Um bei einem Verfahren sowie einer Einrichtung der gattungsgemäßen Art eine Optimierung der Fehlererkennung und Fehlerkorrektur bei gleichzeitiger Minimierung der Kodierungstiefe d. h. der Zahl der nötigen Gatterebenen zu erreichen, wird erfindungsgemäß vorgeschlagen, das Datenwort sowie das Prüfwort in jeweils 4-Bit breite Teilworte aufzuteilen, wobei das Prüfwort aus einer Anzahl von p Prüfbits, und das Datenwort aus einer Anzahl von d Datenbits gebildet ist. Zur Prüfwortgenerierung wird eine d*p Generatormatrix verwendet, bei der jeder Spaltenvektor das Generierungsgewicht Gs = d/4, und jeder Zeilenvektor das Generierungsgewicht Gz = p/4 aufweist, derart, daß zeilenweise jedes Datenbit maximal 2 Bit in einem Prüfteilwort beeinflußt.


    In: 1993.
1992
  • Rückert, Ulrich; Goser, Karl:
    VLSI-Bausteine für neuronale Assoziativ-speicher mit Echtzeit-Anwendungen.
    In: Mikroelektronik für die Informationstechnik, VDE-Verlag, 1992. »»

    conference paper / id: 2285425

  • Rückert, Ulrich; Heimann, D.; Kreuzer, I.; Mostardt, Michael; Pintaske, Christoph; Rüping, Stefan; Surmann, Hartmut; Tryba, V.; Ungering, Ansgar:
    Mikroelektronik der künstlichen neuronalen Netze und der Fuzzy-Systeme.
    In: 20 Jahre Fakultät für Elektrotechnik, 1992. »»

    conference paper / id: 2285432

1991
  • Rückert, Ulrich; Ramacher, Ulrich; Rückert, Ulrich:
    VLSI Design of an Associative Memory based on Distributed Storage of Information.
    In: VLSI Design of Neural Networks, Kluwer Academic Publishers, 1991. »»
    Fulltext (external)

    conference paper / id: 2285192

  • Goser, Karl; Ungering, Ansgar; Surmann, Hartmut; Rückert, Ulrich; Schumacher, Klaus:
    Hardware für Fuzzy-Controller.
    In: Tagungsband des 1. Dortmunder Fuzzy Tag, 1991. »»

    conference paper / id: 2285370

  • Rückert, Ulrich; Milutinovic, V.; Shriver, B.D.:
    An Associative Memory with Neural Architecture and its VLSI Implementation.
    In: Proceedings of the Twenty-Fourth Annual Hawaii International Conference on System Sciences, Volume: 1, IEEE Computer Society Press, 1991. »»
    Abstract

    conference paper / id: 2285419

    An Associative Memory with Neural Architecture and its VLSI Implementation

    Rückert, Ulrich

    Two VLSI special-purpose hardware implementations of an associative memory model are described: a pure digital and a mixed analog/digital architecture. Both architectures can be easily extended to large scale memories with several million storage elements. The advantages and disadvantages of both architectures are pointed out. The memory concept is based on a simple matrix structure with n×m binary elements, the connections, and on distributed storage of information like artificial neural networks. There is no asynchronous feedback and the inputs and outputs are binary, too. Though the system concept is very simple, it has an asymptotic storage capacity of 0.69.m.n bits and the number of patterns that can be stored with low error probability is much larger than the number of columns (artificial neurons). The important aspect for applications is that the input and output patterns have to be sparsely coded


    In: Proceedings of the Twenty-Fourth Annual Hawaii International Conference on System Sciences, Volume: 1, IEEE Computer Society Press, 1991.
  • Ramacher, Ulrich; Rückert, Ulrich:
    VLSI Design of Neural Networks.
    In: Kluwer Academic Publishers, 1991. »»

    book / id: 2280937

  • Palm, Günther; Rückert, Ulrich; Ultsch, Alfred; Brauer, W.; Hernandez, D.:
    Wissensverarbeitung in neuronaler Architektur.
    In: Verteilte Künstliche Intelligenz und kooperatives Arbeiten, Springer-Verlag, 1991. »»
    Fulltext (external)

    conference paper / id: 2285343

  • Goser, Karl; Hilleringmann, Ulrich; Rückert, Ulrich; Monaco, V.A.; Negrini, R.:
    Applications and Implementations of Neural Networks in Microelectronics – Overview and Status.
    In: Advanced Computer Technology, Reliable Sytems and Applications, IEEE Computer Society Press, 1991. »»
    Abstract

    conference paper / id: 2285398

    Applications and Implementations of Neural Networks in Microelectronics – Overview and Status

    Goser, Karl; Hilleringmann, Ulrich; Rückert, Ulrich

    An overview is presented of some of the most important artificial neural networks and their implementation as integrated circuits. The performances of these networks are discussed with regard to the potential of current and future technologies. The overview closes with some possible applications of neural networks in microelectronics


    In: Advanced Computer Technology, Reliable Sytems and Applications, IEEE Computer Society Press, 1991.
  • Ramacher, Ulrich; Rückert, Ulrich; Nossek, J.A.:
    Proceedings 2nd International Conference on Microelectronics for Neural Networks.
    In: Kyrill & Method Verlag, 1991. »»

    conference publication / id: 2285456

  • Schulz, P.; Rückert, Ulrich:
    Implementierung Neuronaler Assoziativ-speicher auf Transputer-Netzwerken.
    In: TOOL91/ RISC91, 1991. »»

    conference paper / id: 2285316

  • Rückert, Ulrich; Czaicki, B.; Heimann, D.; Ramacher, Ulrich:
    Distributed Simulation of Co-operating Neural Networks a Local Area Computer Network.
    In: Microelectronics for Neural Networks, Kyrill & Method Verlag, 1991. »»

    conference paper / id: 2285335

  • Surmann, Hartmut; Kiziloglu, B.; Rückert, Ulrich; Goser, Karl:
    Neural Networks for Defect Recognition on Masks and Integrated Circuits: First Result.
    In: Proceedings of Neuro-Nimes: Neural Networks and their Applications, 1991. »»
    Fulltext (PDF) Fulltext (external)

    conference paper / id: 2285327

  • Rückert, Ulrich; Kleerbaum, C.; Goser, Karl; Delgado-Frias, J.G.; Moore, W.R.:
    Digital VLSI Implementation of an Associative Memory Based on Neural Networks.
    In: VLSI for Artificial Intelligence and Neural Networks, Plenum Press, 1991. »»

    conference paper / id: 2285299

  • Rückert, Ulrich; Surmann, Hartmut; Kohonen, Teuvo:
    Tolerance of a Binary Associative Memory Towards STUCK-AT-FAULTS.
    In: Artificial Neural Networks, Volume: 2, 1991. »»

    conference paper / id: 2285390

  • Soennecken, Arno; Hilleringmann, Ulrich; Rückert, Ulrich; Goser, Karl; Kaesser, A.:
    Analogwertspeicher mit EAROM-Zellen für Neuronale Netze.
    In: Tagungsband des 5. E.I.S.-Workshops, 1991. »»

    conference paper / id: 2285408

1990
  • Rückert, Ulrich:
    Integrationsgerechte Umsetzung von assoziativen Netzwerken mit verteilter Speicherung.
    In: Volume: 130, VDI Verlag, 1990. »»
    Fulltext (external)

    book / id: 2280936

  • Rückert, Ulrich; Goser, Karl; Ramacher, U.; Goser, Karl; Ramacher, Ulrich; Rückert, Ulrich:
    Hybrid VLSI Implementation of an Associative Memory Based on Distributed Storage of Information.
    In: Proceedings of the 1st International Workshop on Microelectronics for Nerual Networks, 1990. »»

    conference paper / id: 2285171

  • Goser, Karl; Rückert, Ulrich:
    Mikroelektronik neuronaler Netze.
    In: ITG-Fachbericht, VDE-Verlag, 1990. »»

    conference paper / id: 2285188

  • Goser, Karl; Ramacher, Ulrich; Rückert, Ulrich:
    Proceedings of the 1st International Workshop on Microelectronics for Neural Networks.
    In: 1990. »»

    conference publication / id: 2285450

  • Goser, Karl; Kreuzer, I.; Rückert, Ulrich; Tryby, V.:
    Chip-Architecturen für künstliche neuronale Netze.
    In: Mikroelektronik, Volume: 5, VDE-Verlag, 1990. »»

    article / id: 2280954

  • Rückert, Ulrich; Almeida, L.B.; Wellekens, C.J.:
    VLSI Implementation of an Associative Memory Based on Distributed Storage of Information.
    In: Neural Networks, Volume: 412, Springer-Verlag, 1990. »»
    Abstract

    conference paper / id: 2285182

    VLSI Implementation of an Associative Memory Based on Distributed Storage of Information

    Rückert, Ulrich

    Two VLSI special-purpose hardware implementations of an associative memory model are described: a pure digital and a mixed analog/digital architecture. Both architectures can be easily extended to large scale memories with several million storage elements. The advantages and disadvantages of both architectures are pointed out. The memory concept is based on a simple matrix structure with n×m binary elements, the connections. There is no asynchronous feedback and the inputs and outputs are binary, too. Though the system concept is very simple, it has an asymptotic storage capacity of 0.69·m·n bits and the number of patterns that can be stored with low error probability is much larger than the number of columns (artificial neurons). The important aspect for applications is that the input and output patterns have to be sparsely coded.


    In: Neural Networks, Volume: 412, Springer-Verlag, 1990.
1989
  • Goser, Karl; Hilleringmann, Ulrich; Rückert, Ulrich; Schumacher, Klaus:
    VLSI Technologies for Artificial Neural Networks.
    In: IEEE Micro, Volume: 9, 1989. »»
    Abstract

    article / id: 2280945

    VLSI Technologies for Artificial Neural Networks

    Goser, Karl; Hilleringmann, Ulrich; Rückert, Ulrich; Schumacher, Klaus

    VLSI systems, basic integrated circuits, and silicon technologies are discussed. Novel circuit and design principles that provide a foundation for the implementation of a wide variety of neural network models in silicon are described. The key issues for a successful integration of neural systems are identified. The realization of algorithms in silicon is examined. Special-purpose hardware for carrying out the activation and transfer function and for the connection elements is discussed. A brief overview of the current silicon technologies is provided.


    In: IEEE Micro, Volume: 9, 1989.
  • Rückert, Ulrich; Goser, Karl:
    Ein digital/analoges Assoziativspeicherkonzept basierend auf neuronalen Strukturen.
    In: GMD-Studie zum 4. E.I.S.-Workshops, 1989. »»

    conference paper / id: 2281030

  • Rückert, Ulrich; Kreuzer, I.; Tryba, V.:
    Fault-Tolerance Of Associative Memories Based On Neural Networks.
    In: Proceedings of the International Conference on Computer Technology, Systems and Applications, 1989. »»
    Abstract

    conference paper / id: 2281072

    Fault-Tolerance Of Associative Memories Based On Neural Networks

    Rückert, Ulrich; Kreuzer, I.; Tryba, V.

    The authors discuss the hardware fault tolerance of associative memories. They study device parameter variations across a chip, which affect essentially the characteristics of analog circuits used by several architectures. The effects of these errors on the performance are examined by means of three typical representatives: the Hopfield model, the self-organizing feature map, and the Boltzmann machine. The authors present a worst-case estimation of the guaranteed fault tolerance of these networks and discuss the consequences for the features of the associative memories. The main result is that the fault tolerance decreases with the number of weights but can be improved by using spare codes or self-organization in connection with added resources


    In: Proceedings of the International Conference on Computer Technology, Systems and Applications, 1989.
  • Rückert, Ulrich; Goser, Karl; Delgado-Frias, J.G.; Moore, W.R.:
    VLSI-Design of Associative Network.
    In: VLSI for Artificial Intelligence, Kluwer Academic Publishers, 1989. »»
    Fulltext (external)

    conference paper / id: 2281084

  • Goser, Karl; Marks, Karl Michael; Rückert, Ulrich:
    Selbstorganisierende Parameterkarten zur Prozeßüberwachung und -voraussage.
    In: 3. Internationaler GI Kongress: Wissensbasierte Systeme, Informatik-Fachberichte, Springer-Verlag, 1989. »»

    conference paper / id: 2281064

1988
  • Tryba, V.; Marks, Karl Michael; Rückert, Ulrich; Goser, Karl:
    Selbstorganisierende Karten als lernende klassifizierende Speicher.
    In: ITG-Fachbericht, VDE-Verlag, 1988. »»

    conference paper / id: 2281009

  • Rückert, Ulrich; Goser, Karl:
    VLSI-Architectures for Associative Networks.
    In: Proceedings of the IEEE International Symposium on Circuits and Systems, Volume: 1, 1988. »»
    Abstract

    conference paper / id: 2281022

    VLSI-Architectures for Associative Networks

    Rückert, Ulrich; Goser, Karl

    This paper describes the basic design principles behind a silicon integrated circuit implementation of Associative Networks (ANs). These principles, which can be used to implement a wide range of AN types, are illustrated by means of a special VLSI design combining analog and digital CMOS technology. The importance of close interaction of system design and technologyresulting ina VLSI concept functionally optimized in m y respects will be pointed out. In this context on-chip analog circuit techniques are presented to implement necessary correlation and threshold operations of the AN processing units. A s e c ~ n d example for functional integration are the mf?mory cells (connection weights, "synapses") by mtrcducing a nonvolatile adaptive memory cell. The proposed cell takes advantage of the floating-ate transistor principle in which a threshold voltage can be set continously over a range of values representing the analog coupling strength of connected processing units.


    In: Proceedings of the IEEE International Symposium on Circuits and Systems, Volume: 1, 1988.
1987
  • Rückert, Ulrich; Goser, Karl; Becker, J.D.; Eisele, I.:
    Adaptive Associative Systems For VLSI.
    In: Lecture Notes in Computer Science, Volume: 253, Springer-Verlag, 1987. »»
    Abstract

    conference paper / id: 2281048

    Adaptive Associative Systems For VLSI

    Rückert, Ulrich; Goser, Karl

    A physical network of an adaptive associative memory is presented. The concept of the network is derived from the Analog Associative Memory due to T. Kohonen and from the Associative Matrix due to G. Palm. The system concept of such a memory is adapted to the VLSI-technique by being partioned into uniform memory slices and by introducing a nonvolatile memory cell. Especially the task of transferring the system concept into technology in order to realize a microelectronic component with new interesting features will be pointed out. The performance of an adaptive associative memory is discussed by means of computer simulations.


    In: Lecture Notes in Computer Science, Volume: 253, Springer-Verlag, 1987.
  • Rückert, Ulrich; Kreuzer, I.; Goser, Karl; Proebster, W.E.; Reiner, H.:
    A VLSI Concept For An Asso-ciative Matrix Based On Neural Networks.
    In: VLSI and Computer, Computer Society Press, 1987. »»

    conference paper / id: 2280973

1986
  • Goser, Karl; Rückert, Ulrich:
    Künstliche Intelligenz - eine Herausforderung an die Großintegrationstechnik.
    In: Nachrichtentechnische Zeitschrift, Volume: 11, 1986. »»

    article / id: 2280942

1985
  • Goser, Karl; Rückert, Ulrich:
    Intelligent VLSI-Memories For Robotics.
    In: Tagungsband, Cognitiva 85, 1985. »»

    conference paper / id: 2280900

1984
  • Goser, Karl; Fölster, C.; Rückert, Ulrich:
    Intelligent Memories in VLSI.
    In: Information Sciences, Volume: 34, 1984. »»
    Abstract

    article / id: 2280870

    Intelligent Memories in VLSI

    Goser, Karl; Fölster, C.; Rückert, Ulrich

    A concept of an intelligent memory, called an adaptive associative system (AAS), is described from the system level down to the device level. The performance of an AAS is discussed by means of computer simulations in regard to text processing and pattern recognition, especially such outstanding features as fault tolerance, semantic association, autosegmentation, and self-organization of information. The system concept of such a memory is rendered adequate for the VLSI technique by partitioning into repetitive memory units and by introducing a nonvolatile memory cell. The importance of interaction in realizing an AAS as a microelectronic component is pointed out for both system design and VLSI technology.


    In: Information Sciences, Volume: 34, 1984.